Commit Graph

162 Commits

Author SHA1 Message Date
Dmitry Eremin-Solenikov
be5e7a7601 arm: basic support for ARMv4/ARMv4T emulation
Currently target-arm/ assumes at least ARMv5 core. Add support for
handling also ARMv4/ARMv4T. This changes the following instructions:

BX(v4T and later)

BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,
MRRC2, PLD QADD, QDADD, QDSUB, QSUB, STRD, SMLAxy, SMLALxy, SMLAWxy,
SMULxy, SMULWxy, STC2 (v5 and later)

All instructions that are "v5TE and later" are also bound to just v5, as
that's how it was before.

This patch doesn _not_ include disabling of cp15 access and base-updated
data abort model (that will be required to emulate chips based on a
ARM7TDMI), because:
* no ARM7TDMI chips are currently emulated (or planned)
* those features aren't strictly necessary for my purposes (SA-1 core
  emulation).

All v5 models are handled as they are v5T. Internally we still have a
check if the model is a v5(T) or v5TE, but as all emulated cores are
v5TE, those two cases are simply aliased (for now).

Patch is heavily based on patch by Filip Navara <filip.navara@gmail.com>
which in turn is based on work by Ulrich Hecht <uli@suse.de> and Vincent
Sanders <vince@kyllikki.org>.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10 00:53:21 +02:00
Peter Maydell
622465e1fa target-arm/helper.c: For float-int conversion helpers pass ints as ints
Correct the argument and return types for the float<->int conversion helper
functions so that integer arguments and return values are declared as
uint32_t/uint64_t, not float32/float64. This allows us to remove the
hand-rolled functions which were doing bitwise copies between the types
via unions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-03 17:19:38 +02:00
Peter Maydell
6aae3df15d target-arm: use make_float32() to make constant floats for VRSQRTS
The preferred way to create a constant floating point value is to use
make_float32() rather than doing a runtime int32_to_float32().
Convert the code in the VRSQRTS helper to work this way.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22 07:59:07 +01:00
Peter Maydell
dda3ec490c target-arm: Fix VRECPS edge cases handling
Correct the handling of edge cases for the VRECPS instruction:
 * this is a Neon instruction so uses the "standard FPSCR value"
 * (zero, inf) is a special case which returns 2.0

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22 07:59:06 +01:00
Peter Maydell
db6e2e65ad target-arm: Fix GE bits for v6media signed modulo arithmetic
Fix the signed modulo arithmetic helpers for the v6media
instructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to set
the GE bits correctly (based on the result of the add or subtract
before it is truncated to 16 bits, not after).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22 07:52:36 +01:00
Adam Lackorzynski
f8bf860605 target-arm: Implement cp15 VA->PA translation
Implement VA->PA translations by cp15-c7 that went through unchanged
previously.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06 23:37:18 +01:00
Christophe Lyon
e07be5d2ae target-arm: fix support for VRSQRTE.
Now use the same algorithm as described in the ARM ARM.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-24 08:53:36 +01:00
Christophe Lyon
fe0e4872e4 target-arm: fix support for VRECPE.
Now use the same algorithm as described in the ARM ARM.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-24 08:53:36 +01:00
Christophe Lyon
56bf4fe297 target-arm: Introduce float64_256 and float64_512 constants.
These two constants will be used by helper functions such as recpe_f32
and rsqrte_f32.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-24 08:53:36 +01:00
Peter Maydell
2d981da77d target-arm: Use standard FPSCR for Neon half-precision operations
The Neon half-precision conversion operations (VCVT.F16.F32 and
VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike
the VFP versions (VCVTB and VCVTT).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10 18:28:30 +01:00
Peter Maydell
fb91678d2c target-arm: Silence NaNs resulting from half-precision conversions
Silence the NaNs that may result from half-precision conversion,
as we do for the other conversions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10 18:28:30 +01:00
Peter Maydell
bb4d4bb376 softfloat: Add float16 type and float16 NaN handling functions
Add a float16 type to softfloat, rather than using bits16 directly.
Also add the missing functions float16_is_quiet_nan(),
float16_is_signaling_nan() and float16_maybe_silence_nan(),
which are needed for the float16 conversion routines.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10 18:28:09 +01:00
Peter Maydell
607b4b0876 target-arm: Clean up handling of MPIDR
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture
as the MPIDR. Clean up its implementation to remove A9 specific handling.

This commit includes fixing an error in the value returned for the
MPIDR on A9, where we were erroneously claiming a cluster ID of 9.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04 21:30:15 +01:00
Peter Maydell
e1bbf44636 target-arm: Add CPU feature flag for v7MP
Add a CPU feature flag for v7MP (the multiprocessing extensions); some
instructions exist only for v7MP and not for the base v7 architecture.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04 21:30:14 +01:00
Peter Maydell
39ea3d4eaf target-arm: Don't generate code specific to current CPU mode for SRS
When translating the SRS instruction, handle the "store registers
to stack of current mode" case in the helper function rather than
inline. This means the generated code does not make assumptions
about the current CPU mode which might not be valid when the TB
is executed later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Peter Maydell
718269667a target-arm: Use the standard FPSCR value for VRSQRTS
VSQRTS always uses the standard FPSCR value as it is a Neon instruction.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Peter Maydell
3a492f3a60 target-arm: Add support for 'Standard FPSCR Value' as used by Neon
Add support to the ARM helper routines for a second fp_status value
which should be used for operations which the ARM ARM indicates use
"ARM standard floating-point arithmetic" rather than being controlled
by the rounding/flush/NaN settings in the FPSCR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Peter Maydell
9ea62f571c target-arm: Fix implementation of VRSQRTS
The implementation of the ARM VRSQRTS instruction (which calculates
(3 - op1 * op2) / 2) was missing the division operation. It also
did not handle the special cases of (0,inf) and (inf,0).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Peter Maydell
cecd8504b8 target-arm: wire up the softfloat flush_input_to_zero flag
Wire up the new softfloat support for flushing input denormals
to zero on ARM. The FPSCR FZ bit enables flush-to-zero for
both inputs and outputs, but the reporting of when inputs are
flushed to zero is via a separate IDC bit rather than the UFC
(underflow) bit used when output denormals are flushed to zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06 22:16:59 +01:00
Peter Maydell
b12c390b91 target-arm: Set softfloat cumulative exc flags from correct FPSCR bits
When handling a write to the ARM FPSCR, set the softfloat cumulative
exception flags from the cumulative flags in the FPSCR, not the
exception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host
will only look at the correct bits anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06 22:16:59 +01:00
Juha Riihimäki
16440c5fa0 target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:21:17 +01:00
Mattias Holm
9c486ad6e4 target-arm: correct cp15 c1_sys reset value for cortex-a8
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:21:17 +01:00
Juha Riihimäki
c003432809 target-arm: fix vmsav6 access control
Override access control checks (including execute) for mmu translation
table descriptors assigned to manager domains.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:21:16 +01:00
Peter Maydell
72f24d155c ARM: Implement VCVT to 16 bit integer using new softfloat routines
Use the softfloat conversion routines for conversion to 16 bit
integers, because just casting to a 16 bit type truncates the
value rather than saturating it at 16-bit MAXINT/MININT.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
26a5e69aaf ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed point
VCVT of 16 bit fixed point to float should ignore the top 16 bits
of the source register. Cast to int16_t and friends rather than
int16 -- the former is guaranteed exactly 16 bits wide where the
latter is merely at least 16 bits wide (and so is usually 32 bits).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
2d6277373d ARM: Return correct result for single<->double conversion of NaN
The ARM ARM defines that if the input to a single<->double conversion
is a NaN then the output is always forced to be a quiet NaN by setting
the most significant bit of the fraction part.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
09d9487fbb ARM: Return correct result for float-to-integer conversion of NaN
The ARM architecture mandates that converting a NaN value to
integer gives zero (if Invalid Operation FP exceptions are
not being trapped). This isn't the behaviour of the SoftFloat
library, so NaNs must be special-cased.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
0165329578 ARM: Expose vfp_get_fpscr() and vfp_set_fpscr() to C code
Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to C
code as well as generated code, so we can use them to read and
write the FPSCR when saving and restoring VFP registers across
signal handlers in linux-user mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-12-03 15:09:39 +02:00
Peter Maydell
3a807decfa ARM: enable XScale/iWMMXT in linux-user mode
In linux-user mode, the XScale/iWMMXT coprocessors must be enabled
at reset so that we can run code that uses these instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2010-12-03 15:09:39 +02:00
Stefan Weil
9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Chih-Min Chao
4c4fd3f852 target-arm : fix parallel saturated subtraction implementation
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 23:45:29 +02:00
Lars Munch
e03c22a98c arm: fix arm kernel boot for non zero start addr
Booting an arm kernel has been broken a while when booting from non zero start
address. This is due to the order of events: board init loads the kernel and
sets register 15 to the start address and then qemu_system_reset reset the cpu
making register 15 zero again.

This patch fixes the usage of the register 15 start address trick in
combination with arm_load_kernel.

Signed-off-by: Lars Munch <lars@segv.dk>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-31 19:40:41 +02:00
Paul Brook
4f78c9ad5a Fix arm-linux-user
Only include hw/loader.h from target-arm/helper.c when building for
system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-05 19:56:34 +01:00
Paul Brook
983fe82611 ARMv7-M reset fixes
Move ARMv7-M PC/SP initialization to the CPU reset routine.  Add a board
reset routine to call this.  Also load values directly from ROM as
images have not been copied yet.

Avoid clearing the NVIC pointer on cpu reset.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-05 19:43:12 +01:00
Rabin Vincent
3ad493fc5e target-arm: disable PAGE_EXEC for XN pages
Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection
checking if the page is already in the TLB.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27 14:14:34 +01:00
Paul Brook
d4c430a80f Large page TLB flush
QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page.  However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.

Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages.  If the guest invalidates this region then flush the
whole TLB.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-17 02:44:41 +00:00
Paul Brook
4fcc562bff Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:25 +00:00
Rabin Vincent
30a8cac139 target-arm: support thumb exception handlers
When handling an exception, switch to the correct mode based on the
Thumb Exception (TE) bit in the SCTLR.

Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-19 15:20:21 +00:00
Riku Voipio
3f26c1227e target-arm: refactor cp15.c13 register access
Access the cp15.c13 TLS registers directly with TCG ops instead of with
a slow helper. If the the cp15 read/write was not TLS register access,
fall back to the cp15 helper.

This makes accessing __thread variables in linux-user when apps are compiled
with -mtp=cp15 possible. legal cp15 register to acces from linux-user are
already checked in cp15_user_ok.

While at it, make the cp15.c13 Thread ID registers available only on
ARMv6K and newer.

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-02-06 17:19:43 +01:00
Paul Brook
426f5abcaa ARM atomic ops rewrite
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-22 21:35:13 +00:00
Paul Brook
100555620f ARM Cortex-A9 cpu support
Basic Cortex-A9 support.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19 16:45:20 +00:00
Paul Brook
600114988c ARM FP16 support
Implement the ARM VFP half precision floating point extensions.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19 16:45:20 +00:00
Juha Riihimäki
71b3c3dea2 target-arm: allow modifying vfp fpexc en bit only
All other bits except for the EN in the VFP FPEXC register are defined
as subarchitecture specific and real functionality for any of the
other bits has not been implemented in QEMU. However, current code
allows modifying all bits in the VFP FPEXC register leading to
problems when guest code is writing 1's to the subarchitecture
specific bits and checking whether the bits stay up to verify the
existence of functionality which in fact does not exist in QEMU.
This patch has been revised to include the same behavior change in
the gdb register write function.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Aurelien Jarno
686eeb93d5 target-arm: fix sdiv helper
(INT32_MIN / -1) triggers an overflow, and the result depends on the
host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a
test to output the correct value.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-23 00:05:17 +02:00
Aurelien Jarno
7bbcb0afe7 target-arm: use clz32() instead of a for loop
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-23 00:05:17 +02:00
Anthony Liguori
c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc
99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
aliguori
0bf46a40a1 qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24 18:03:41 +00:00
aurel32
533d177a98 Fix correct reset value for ARM CP15 c1 auxiliary control register
According to ARM Cortex A8 Technical Reference Manual, the reset value for CP15 c1 auxiliary control
register is 2, not zero (page 3.12).

Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6771 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 22:10:28 +00:00
aurel32
2b3ea3154d clean build: Fix arm build warnings
Fix remaining arm warnings - except for the mess in the NetWinder FP
emulator.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6766 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 21:48:00 +00:00
aliguori
0d0266a53b targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05 22:06:11 +00:00
aliguori
eca1bdf415 Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26 19:54:31 +00:00
pbrook
fe76d97653 Implement flush-to-zero mode (denormal results are replaced with zero).
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6107 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19 14:33:59 +00:00
pbrook
5c7908ed23 Implement default-NaN mode.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6106 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19 13:53:37 +00:00
pbrook
a49ea279c4 Implement ARMv7 cp15 cache ID registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19 13:37:53 +00:00
pbrook
fe1479c3ad Implement (very) basic Thumb2-EE support. This doesn't actually implement
EE state, just the associated system coprocessor registers.  It is sufficient
to keep OS setup and context switching code happy.

Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6104 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19 13:18:36 +00:00
pbrook
644ad8066d Fix VFP fixed point conversion routines.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19 13:02:08 +00:00
pbrook
d4934d18f3 Implement ARMv7 MMU access permissions.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6099 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-19 12:39:00 +00:00
pbrook
b2fa17977f Fix ARMv6 translation table base address calculation.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-22 19:22:30 +00:00
pbrook
4be27dbbde Optimize redundant cp15 coprocessor access control register writes.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5512 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-22 16:14:08 +00:00
pbrook
56aebc8916 Add GDB XML register description support.
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5459 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-11 17:55:29 +00:00
balrog
a87aa10b85 ARMv6: fix SIMD add/sub carry flags (Vincent Palatin).
After a quick code review, it seems to be a bad cut-n-paste between
16-bit and 8-bit UADD/USUB, indeed UADD8/USUB8 tries to set GE bits by
pair instead of one at a time.
Besides, the addition operations (UADD8/UADD16) set GE bits to "NOT
carry" instead of "carry" (probably once again due to a copy of the
substraction code which sets flags to "NOT borrow")


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4900 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-19 10:46:13 +00:00
balrog
22478e79f2 Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).
helper.c
 - copy reference c0_c2 to runtime c0_c2 and not c0_c1

op_helper.c
 - remove old code (PARAM1, probably some left over from old dyngen)
   that broke do_[us]sat

translate.c
 - gen_smul_dual should sign-extend from 16 bit to 32 bit and not from
   8 to 32
 - disas_arm_insn:
   * smlalxy:  that was completely wrong;  now the addition is
     performed as for smlald
   * pkhtb:  optional ASR not taken into account (similar
   * to [us]sat)
   * pkhtb/pkhbt: tmp2 is dead
   * smlald, smlsld, smuad, smusd, smlad, smlsd: rd
   * and rn swapped


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4898 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-19 10:12:22 +00:00
pbrook
ab19b0ecfd ARMv7-M interrupt stack alignment fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4823 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-02 16:44:09 +00:00
pbrook
460a09c1fb Fix incorrect argument types.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4291 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-01 12:04:35 +00:00
balrog
601d70b9e5 Remove an unused field and fix some non-code typos.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-20 01:03:45 +00:00
balrog
66230e0dee Correct more ARM VFP 32/64 and signed/unsigned typos.
Fixes unreadable fonts in Maemo guest.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4221 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-20 00:58:01 +00:00
balrog
827df9f3c5 Add basic OMAP2 chip support.
Add the OMAP242x (arm1136 core) initialisation with basic on-chip
peripherals and update OMAP1 peripherals which are re-used in OMAP2.
Make palmte.c and sd.c errors go to stderr.
Allow disabling SD chipselect.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4213 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-14 21:05:22 +00:00
balrog
6c95676b16 Store the right TCG temp (typo).
Stops ARMv6 target from segfaulting early.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4201 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-13 00:57:49 +00:00
aurel32
ca10f86763 Remove osdep.c/qemu-img code duplication
(Kevin Wolf)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-11 21:35:42 +00:00
aurel32
1654b2d6bf Fix few spelling issues in comments
(Stefan Weil)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4187 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-11 04:55:07 +00:00
pbrook
6fbe23d50e ARM N=Z=1 flag fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-01 17:19:11 +00:00
pbrook
ad69471ce5 ARM TCG conversion 14/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4151 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:48:30 +00:00
pbrook
8f8e3aa451 ARM TCG conversion 13/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4150 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:48:01 +00:00
pbrook
8984bd2e83 ARM TCG conversion 12/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4149 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:47:48 +00:00
pbrook
5e3f878ad6 ARM TCG conversion 11/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4148 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:47:34 +00:00
pbrook
4373f3ceeb ARM TCG conversion 10/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4147 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:47:19 +00:00
pbrook
b010980544 ARM TCG conversion 9/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:47:03 +00:00
pbrook
6ddbc6e4cf ARM TCG conversion 7/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:46:33 +00:00
pbrook
3670669ce2 ARM TCG conversion 6/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4143 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:46:19 +00:00
pbrook
1497c961af ARM TCG conversion 4/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4141 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:45:50 +00:00
pbrook
f51bbbfefe ARM TCG conversion 2/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4139 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:45:13 +00:00
pbrook
b26eefb68e ARM TCG conversion 1/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4138 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-31 03:44:26 +00:00
ths
01ba98161f Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3778 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-09 02:22:57 +00:00
pbrook
2ad207d4a0 Thumb semihosting fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3729 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-24 23:22:11 +00:00
balrog
2f4a40e569 Prevent cpsr_write/_read be put out of line in op.o (fixes a segfault on some platforms).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3633 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-13 01:50:15 +00:00
pbrook
9ee6e8bb85 ARMv7 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11 00:04:49 +00:00
bellard
aaed909a49 added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10 15:15:54 +00:00
balrog
405ee3ad57 Invalidate TLBs when domains are changed (Matthew Warton).
Legalise cp15 pid register writes (Matthew Warton).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3494 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-31 00:47:13 +00:00
j_mayer
6ebbf39000 Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14 07:07:08 +00:00
j_mayer
c732abe222 Unify '-cpu ?' option.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-12 06:47:46 +00:00
ths
5fafdf24ef find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16 21:08:06 +00:00
balrog
2e23213f26 Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3107 c046a42c-6fe2-441c-8c8c-71466251a162
2007-08-01 02:31:54 +00:00
balrog
330c4d61a6 Fix XScale MMU's extended small pages.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3093 c046a42c-6fe2-441c-8c8c-71466251a162
2007-07-29 22:21:45 +00:00
balrog
c3d2689d88 Basic OMAP310 support. Basic Palm Tungsten|E machine emulation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3091 c046a42c-6fe2-441c-8c8c-71466251a162
2007-07-29 17:57:26 +00:00
balrog
610c3c8afd Reset ARM cp15.c1_sys to default values. Fix XScale cp15 accesses.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3013 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-24 12:09:48 +00:00
pbrook
ce8198612e ARM946 CPU support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2783 c046a42c-6fe2-441c-8c8c-71466251a162
2007-05-08 02:30:40 +00:00
balrog
18c9b56060 Implement iwMMXt instruction set for the PXA270 cpu.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2752 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-30 02:02:17 +00:00
balrog
c1713132e0 Core features of ARM XScale processors. Main PXA270 and PXA255 peripherals.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2749 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-30 01:26:42 +00:00
pbrook
c73c3aa081 Fix ARM fine pagetables.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2742 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-29 19:06:34 +00:00