Implement iwMMXt instruction set for the PXA270 cpu.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2752 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
a171fe394a
commit
18c9b56060
@ -129,6 +129,14 @@ typedef struct CPUARMState {
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float_status fp_status;
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} vfp;
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/* iwMMXt coprocessor state. */
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struct {
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uint64_t regs[16];
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uint64_t val;
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uint32_t cregs[16];
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} iwmmxt;
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#if defined(CONFIG_USER_ONLY)
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/* For usermode syscall translation. */
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int eabi;
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@ -218,10 +226,21 @@ enum arm_cpu_mode {
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#define ARM_VFP_FPINST 9
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#define ARM_VFP_FPINST2 10
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/* iwMMXt coprocessor control registers. */
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#define ARM_IWMMXT_wCID 0
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#define ARM_IWMMXT_wCon 1
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#define ARM_IWMMXT_wCSSF 2
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#define ARM_IWMMXT_wCASF 3
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#define ARM_IWMMXT_wCGR0 8
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#define ARM_IWMMXT_wCGR1 9
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#define ARM_IWMMXT_wCGR2 10
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#define ARM_IWMMXT_wCGR3 11
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enum arm_features {
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ARM_FEATURE_VFP,
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ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
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ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
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ARM_FEATURE_IWMMXT /* Intel iwMMXt extension. */
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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@ -32,6 +32,8 @@ register uint32_t T2 asm(AREG3);
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#define FT0d env->vfp.tmp0d
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#define FT1d env->vfp.tmp1d
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#define M0 env->iwmmxt.val
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#include "cpu.h"
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#include "exec-all.h"
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@ -42,6 +42,8 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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case ARM_CPUID_PXA270_C5:
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set_feature(env, ARM_FEATURE_XSCALE);
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/* JTAG_ID is ((id << 28) | 0x09265013) */
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set_feature(env, ARM_FEATURE_IWMMXT);
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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env->cp15.c0_cachetype = 0xd172172;
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break;
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default:
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@ -1213,3 +1213,6 @@ void OPPROTO op_movl_T0_T2(void)
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{
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T0 = T2;
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}
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/* iwMMXt support */
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#include "op_iwmmxt.c"
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707
target-arm/op_iwmmxt.c
Normal file
707
target-arm/op_iwmmxt.c
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@ -0,0 +1,707 @@
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/*
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* iwMMXt micro operations for XScale.
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*
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* Copyright (c) 2007 OpenedHand, Ltd.
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define M1 env->iwmmxt.regs[PARAM1]
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/* iwMMXt macros extracted from GNU gdb. */
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/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */
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#define SIMD8_SET( v, n, b) ((v != 0) << ((((b) + 1) * 4) + (n)))
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#define SIMD16_SET(v, n, h) ((v != 0) << ((((h) + 1) * 8) + (n)))
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#define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n)))
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#define SIMD64_SET(v, n) ((v != 0) << (32 + (n)))
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/* Flags to pass as "n" above. */
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#define SIMD_NBIT -1
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#define SIMD_ZBIT -2
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#define SIMD_CBIT -3
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#define SIMD_VBIT -4
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/* Various status bit macros. */
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#define NBIT8(x) ((x) & 0x80)
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#define NBIT16(x) ((x) & 0x8000)
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#define NBIT32(x) ((x) & 0x80000000)
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#define NBIT64(x) ((x) & 0x8000000000000000ULL)
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#define ZBIT8(x) (((x) & 0xff) == 0)
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#define ZBIT16(x) (((x) & 0xffff) == 0)
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#define ZBIT32(x) (((x) & 0xffffffff) == 0)
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#define ZBIT64(x) (x == 0)
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/* Sign extension macros. */
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#define EXTEND8H(a) ((uint16_t) (int8_t) (a))
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#define EXTEND8(a) ((uint32_t) (int8_t) (a))
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#define EXTEND16(a) ((uint32_t) (int16_t) (a))
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#define EXTEND16S(a) ((int32_t) (int16_t) (a))
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#define EXTEND32(a) ((uint64_t) (int32_t) (a))
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void OPPROTO op_iwmmxt_movl_T0_T1_wRn(void)
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{
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T0 = M1 & ~(uint32_t) 0;
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T1 = M1 >> 32;
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}
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void OPPROTO op_iwmmxt_movl_wRn_T0_T1(void)
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{
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M1 = ((uint64_t) T1 << 32) | T0;
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}
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void OPPROTO op_iwmmxt_movq_M0_wRn(void)
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{
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M0 = M1;
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}
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void OPPROTO op_iwmmxt_orq_M0_wRn(void)
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{
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M0 |= M1;
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}
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void OPPROTO op_iwmmxt_andq_M0_wRn(void)
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{
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M0 &= M1;
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}
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void OPPROTO op_iwmmxt_xorq_M0_wRn(void)
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{
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M0 ^= M1;
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}
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void OPPROTO op_iwmmxt_maddsq_M0_wRn(void)
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{
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M0 = ((
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EXTEND16S((M0 >> 0) & 0xffff) * EXTEND16S((M1 >> 0) & 0xffff) +
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EXTEND16S((M0 >> 16) & 0xffff) * EXTEND16S((M1 >> 16) & 0xffff)
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) & 0xffffffff) | ((uint64_t) (
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EXTEND16S((M0 >> 32) & 0xffff) * EXTEND16S((M1 >> 32) & 0xffff) +
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EXTEND16S((M0 >> 48) & 0xffff) * EXTEND16S((M1 >> 48) & 0xffff)
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) << 32);
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}
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void OPPROTO op_iwmmxt_madduq_M0_wRn(void)
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{
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M0 = ((
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((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) +
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((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)
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) & 0xffffffff) | ((
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((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) +
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((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)
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) << 32);
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}
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void OPPROTO op_iwmmxt_sadb_M0_wRn(void)
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{
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#define abs(x) (((x) >= 0) ? x : -x)
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#define SADB(SHR) abs((int) ((M0 >> SHR) & 0xff) - (int) ((M1 >> SHR) & 0xff))
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M0 =
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SADB(0) + SADB(8) + SADB(16) + SADB(24) +
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SADB(32) + SADB(40) + SADB(48) + SADB(56);
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#undef SADB
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}
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void OPPROTO op_iwmmxt_sadw_M0_wRn(void)
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{
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#define SADW(SHR) \
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abs((int) ((M0 >> SHR) & 0xffff) - (int) ((M1 >> SHR) & 0xffff))
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M0 = SADW(0) + SADW(16) + SADW(32) + SADW(48);
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#undef SADW
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}
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void OPPROTO op_iwmmxt_addl_M0_wRn(void)
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{
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M0 += env->iwmmxt.regs[PARAM1] & 0xffffffff;
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}
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void OPPROTO op_iwmmxt_mulsw_M0_wRn(void)
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{
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#define MULS(SHR) ((uint64_t) ((( \
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EXTEND16S((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff) \
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) >> PARAM2) & 0xffff) << SHR)
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M0 = MULS(0) | MULS(16) | MULS(32) | MULS(48);
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#undef MULS
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}
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void OPPROTO op_iwmmxt_muluw_M0_wRn(void)
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{
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#define MULU(SHR) ((uint64_t) ((( \
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((M0 >> SHR) & 0xffff) * ((M1 >> SHR) & 0xffff) \
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) >> PARAM2) & 0xffff) << SHR)
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M0 = MULU(0) | MULU(16) | MULU(32) | MULU(48);
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#undef MULU
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}
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void OPPROTO op_iwmmxt_macsw_M0_wRn(void)
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{
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#define MACS(SHR) ( \
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EXTEND16((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff))
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M0 = (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48));
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#undef MACS
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}
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void OPPROTO op_iwmmxt_macuw_M0_wRn(void)
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{
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#define MACU(SHR) ( \
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(uint32_t) ((M0 >> SHR) & 0xffff) * \
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(uint32_t) ((M1 >> SHR) & 0xffff))
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M0 = MACU(0) + MACU(16) + MACU(32) + MACU(48);
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#undef MACU
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}
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void OPPROTO op_iwmmxt_addsq_M0_wRn(void)
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{
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M0 = (int64_t) M0 + (int64_t) M1;
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}
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void OPPROTO op_iwmmxt_adduq_M0_wRn(void)
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{
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M0 += M1;
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}
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void OPPROTO op_iwmmxt_movq_wRn_M0(void)
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{
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M1 = M0;
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}
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void OPPROTO op_iwmmxt_movl_wCx_T0(void)
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{
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env->iwmmxt.cregs[PARAM1] = T0;
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}
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void OPPROTO op_iwmmxt_movl_T0_wCx(void)
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{
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T0 = env->iwmmxt.cregs[PARAM1];
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}
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void OPPROTO op_iwmmxt_movl_T1_wCx(void)
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{
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T1 = env->iwmmxt.cregs[PARAM1];
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}
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void OPPROTO op_iwmmxt_set_mup(void)
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{
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env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 2;
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}
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void OPPROTO op_iwmmxt_set_cup(void)
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{
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env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 1;
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}
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void OPPROTO op_iwmmxt_setpsr_nz(void)
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{
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
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SIMD64_SET((M0 == 0), SIMD_ZBIT) |
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SIMD64_SET((M0 & (1ULL << 63)), SIMD_NBIT);
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}
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void OPPROTO op_iwmmxt_negq_M0(void)
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{
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M0 = ~M0;
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}
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#define NZBIT8(x, i) \
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SIMD8_SET(NBIT8((x) & 0xff), SIMD_NBIT, i) | \
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SIMD8_SET(ZBIT8((x) & 0xff), SIMD_ZBIT, i)
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#define NZBIT16(x, i) \
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SIMD16_SET(NBIT16((x) & 0xffff), SIMD_NBIT, i) | \
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SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
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#define NZBIT32(x, i) \
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SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
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SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
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#define NZBIT64(x) \
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SIMD64_SET(NBIT64(x), SIMD_NBIT) | \
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SIMD64_SET(ZBIT64(x), SIMD_ZBIT)
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#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, b_M0_wRn))(void) \
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{ \
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M0 = \
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(((M0 >> SH0) & 0xff) << 0) | (((M1 >> SH0) & 0xff) << 8) | \
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(((M0 >> SH1) & 0xff) << 16) | (((M1 >> SH1) & 0xff) << 24) | \
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(((M0 >> SH2) & 0xff) << 32) | (((M1 >> SH2) & 0xff) << 40) | \
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(((M0 >> SH3) & 0xff) << 48) | (((M1 >> SH3) & 0xff) << 56); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
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NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \
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NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \
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NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \
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NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \
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} \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, w_M0_wRn))(void) \
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{ \
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M0 = \
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(((M0 >> SH0) & 0xffff) << 0) | \
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(((M1 >> SH0) & 0xffff) << 16) | \
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(((M0 >> SH2) & 0xffff) << 32) | \
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(((M1 >> SH2) & 0xffff) << 48); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
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NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 16, 1) | \
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NZBIT8(M0 >> 32, 2) | NZBIT8(M0 >> 48, 3); \
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} \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, l_M0_wRn))(void) \
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{ \
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M0 = \
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(((M0 >> SH0) & 0xffffffff) << 0) | \
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(((M1 >> SH0) & 0xffffffff) << 32); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
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NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \
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} \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, ub_M0))(void) \
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{ \
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M0 = \
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(((M0 >> SH0) & 0xff) << 0) | \
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(((M0 >> SH1) & 0xff) << 16) | \
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(((M0 >> SH2) & 0xff) << 32) | \
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(((M0 >> SH3) & 0xff) << 48); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
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NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \
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NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \
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} \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, uw_M0))(void) \
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{ \
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M0 = \
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(((M0 >> SH0) & 0xffff) << 0) | \
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(((M0 >> SH2) & 0xffff) << 32); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
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NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \
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} \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, ul_M0))(void) \
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{ \
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M0 = (((M0 >> SH0) & 0xffffffff) << 0); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \
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} \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, sb_M0))(void) \
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{ \
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M0 = \
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((uint64_t) EXTEND8H((M0 >> SH0) & 0xff) << 0) | \
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((uint64_t) EXTEND8H((M0 >> SH1) & 0xff) << 16) | \
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((uint64_t) EXTEND8H((M0 >> SH2) & 0xff) << 32) | \
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((uint64_t) EXTEND8H((M0 >> SH3) & 0xff) << 48); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
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NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \
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NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \
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} \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, sw_M0))(void) \
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{ \
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M0 = \
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((uint64_t) EXTEND16((M0 >> SH0) & 0xffff) << 0) | \
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((uint64_t) EXTEND16((M0 >> SH2) & 0xffff) << 32); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
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NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \
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} \
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void OPPROTO glue(op_iwmmxt_unpack, glue(S, sl_M0))(void) \
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{ \
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M0 = EXTEND32((M0 >> SH0) & 0xffffffff); \
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env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \
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}
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IWMMXT_OP_UNPACK(l, 0, 8, 16, 24)
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IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)
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#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \
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void OPPROTO glue(op_iwmmxt_, glue(SUFF, b_M0_wRn))(void) \
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{ \
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M0 = \
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CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) | \
|
||||
CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) | \
|
||||
CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) | \
|
||||
CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff); \
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
|
||||
NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \
|
||||
NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \
|
||||
NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \
|
||||
NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \
|
||||
} \
|
||||
void OPPROTO glue(op_iwmmxt_, glue(SUFF, w_M0_wRn))(void) \
|
||||
{ \
|
||||
M0 = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \
|
||||
CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff); \
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
|
||||
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \
|
||||
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \
|
||||
} \
|
||||
void OPPROTO glue(op_iwmmxt_, glue(SUFF, l_M0_wRn))(void) \
|
||||
{ \
|
||||
M0 = CMP(0, Tl, O, 0xffffffff) | \
|
||||
CMP(32, Tl, O, 0xffffffff); \
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
|
||||
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \
|
||||
}
|
||||
#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
|
||||
(TYPE) ((M1 >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)
|
||||
IWMMXT_OP_CMP(cmpeq, uint8_t, uint16_t, uint32_t, ==)
|
||||
IWMMXT_OP_CMP(cmpgts, int8_t, int16_t, int32_t, >)
|
||||
IWMMXT_OP_CMP(cmpgtu, uint8_t, uint16_t, uint32_t, >)
|
||||
#undef CMP
|
||||
#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
|
||||
(TYPE) ((M1 >> SHR) & MASK)) ? M0 : M1) & ((uint64_t) MASK << SHR))
|
||||
IWMMXT_OP_CMP(mins, int8_t, int16_t, int32_t, <)
|
||||
IWMMXT_OP_CMP(minu, uint8_t, uint16_t, uint32_t, <)
|
||||
IWMMXT_OP_CMP(maxs, int8_t, int16_t, int32_t, >)
|
||||
IWMMXT_OP_CMP(maxu, uint8_t, uint16_t, uint32_t, >)
|
||||
#undef CMP
|
||||
#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
|
||||
OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR)
|
||||
IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -)
|
||||
IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +)
|
||||
#undef CMP
|
||||
/* TODO Signed- and Unsigned-Saturation */
|
||||
#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
|
||||
OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR)
|
||||
IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -)
|
||||
IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +)
|
||||
IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -)
|
||||
IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)
|
||||
#undef CMP
|
||||
#undef IWMMXT_OP_CMP
|
||||
|
||||
void OPPROTO op_iwmmxt_avgb_M0_wRn(void)
|
||||
{
|
||||
#define AVGB(SHR) ((( \
|
||||
((M0 >> SHR) & 0xff) + ((M1 >> SHR) & 0xff) + PARAM2) >> 1) << SHR)
|
||||
M0 =
|
||||
AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) |
|
||||
AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
SIMD8_SET(ZBIT8((M0 >> 0) & 0xff), SIMD_ZBIT, 0) |
|
||||
SIMD8_SET(ZBIT8((M0 >> 8) & 0xff), SIMD_ZBIT, 1) |
|
||||
SIMD8_SET(ZBIT8((M0 >> 16) & 0xff), SIMD_ZBIT, 2) |
|
||||
SIMD8_SET(ZBIT8((M0 >> 24) & 0xff), SIMD_ZBIT, 3) |
|
||||
SIMD8_SET(ZBIT8((M0 >> 32) & 0xff), SIMD_ZBIT, 4) |
|
||||
SIMD8_SET(ZBIT8((M0 >> 40) & 0xff), SIMD_ZBIT, 5) |
|
||||
SIMD8_SET(ZBIT8((M0 >> 48) & 0xff), SIMD_ZBIT, 6) |
|
||||
SIMD8_SET(ZBIT8((M0 >> 56) & 0xff), SIMD_ZBIT, 7);
|
||||
#undef AVGB
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_avgw_M0_wRn(void)
|
||||
{
|
||||
#define AVGW(SHR) ((( \
|
||||
((M0 >> SHR) & 0xffff) + ((M1 >> SHR) & 0xffff) + PARAM2) >> 1) << SHR)
|
||||
M0 = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
SIMD16_SET(ZBIT16((M0 >> 0) & 0xffff), SIMD_ZBIT, 0) |
|
||||
SIMD16_SET(ZBIT16((M0 >> 16) & 0xffff), SIMD_ZBIT, 1) |
|
||||
SIMD16_SET(ZBIT16((M0 >> 32) & 0xffff), SIMD_ZBIT, 2) |
|
||||
SIMD16_SET(ZBIT16((M0 >> 48) & 0xffff), SIMD_ZBIT, 3);
|
||||
#undef AVGW
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_msadb_M0_wRn(void)
|
||||
{
|
||||
M0 = ((((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) +
|
||||
((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)) & 0xffffffff) |
|
||||
((((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) +
|
||||
((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)) << 32);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_align_M0_T0_wRn(void)
|
||||
{
|
||||
M0 >>= T0 << 3;
|
||||
M0 |= M1 << (64 - (T0 << 3));
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_insr_M0_T0_T1(void)
|
||||
{
|
||||
M0 &= ~((uint64_t) T1 << PARAM1);
|
||||
M0 |= (uint64_t) (T0 & T1) << PARAM1;
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_extrsb_T0_M0(void)
|
||||
{
|
||||
T0 = EXTEND8((M0 >> PARAM1) & 0xff);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_extrsw_T0_M0(void)
|
||||
{
|
||||
T0 = EXTEND16((M0 >> PARAM1) & 0xffff);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_extru_T0_M0_T1(void)
|
||||
{
|
||||
T0 = (M0 >> PARAM1) & T1;
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_bcstb_M0_T0(void)
|
||||
{
|
||||
T0 &= 0xff;
|
||||
M0 =
|
||||
((uint64_t) T0 << 0) | ((uint64_t) T0 << 8) |
|
||||
((uint64_t) T0 << 16) | ((uint64_t) T0 << 24) |
|
||||
((uint64_t) T0 << 32) | ((uint64_t) T0 << 40) |
|
||||
((uint64_t) T0 << 48) | ((uint64_t) T0 << 56);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_bcstw_M0_T0(void)
|
||||
{
|
||||
T0 &= 0xffff;
|
||||
M0 =
|
||||
((uint64_t) T0 << 0) | ((uint64_t) T0 << 16) |
|
||||
((uint64_t) T0 << 32) | ((uint64_t) T0 << 48);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_bcstl_M0_T0(void)
|
||||
{
|
||||
M0 = ((uint64_t) T0 << 0) | ((uint64_t) T0 << 32);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_addcb_M0(void)
|
||||
{
|
||||
M0 =
|
||||
((M0 >> 0) & 0xff) + ((M0 >> 8) & 0xff) +
|
||||
((M0 >> 16) & 0xff) + ((M0 >> 24) & 0xff) +
|
||||
((M0 >> 32) & 0xff) + ((M0 >> 40) & 0xff) +
|
||||
((M0 >> 48) & 0xff) + ((M0 >> 56) & 0xff);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_addcw_M0(void)
|
||||
{
|
||||
M0 =
|
||||
((M0 >> 0) & 0xffff) + ((M0 >> 16) & 0xffff) +
|
||||
((M0 >> 32) & 0xffff) + ((M0 >> 48) & 0xffff);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_addcl_M0(void)
|
||||
{
|
||||
M0 = (M0 & 0xffffffff) + (M0 >> 32);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_msbb_T0_M0(void)
|
||||
{
|
||||
T0 =
|
||||
((M0 >> 7) & 0x01) | ((M0 >> 14) & 0x02) |
|
||||
((M0 >> 21) & 0x04) | ((M0 >> 28) & 0x08) |
|
||||
((M0 >> 35) & 0x10) | ((M0 >> 42) & 0x20) |
|
||||
((M0 >> 49) & 0x40) | ((M0 >> 56) & 0x80);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_msbw_T0_M0(void)
|
||||
{
|
||||
T0 =
|
||||
((M0 >> 15) & 0x01) | ((M0 >> 30) & 0x02) |
|
||||
((M0 >> 45) & 0x04) | ((M0 >> 52) & 0x08);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_msbl_T0_M0(void)
|
||||
{
|
||||
T0 = ((M0 >> 31) & 0x01) | ((M0 >> 62) & 0x02);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_srlw_M0_T0(void)
|
||||
{
|
||||
M0 =
|
||||
(((M0 & (0xffffll << 0)) >> T0) & (0xffffll << 0)) |
|
||||
(((M0 & (0xffffll << 16)) >> T0) & (0xffffll << 16)) |
|
||||
(((M0 & (0xffffll << 32)) >> T0) & (0xffffll << 32)) |
|
||||
(((M0 & (0xffffll << 48)) >> T0) & (0xffffll << 48));
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
|
||||
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_srll_M0_T0(void)
|
||||
{
|
||||
M0 =
|
||||
((M0 & (0xffffffffll << 0)) >> T0) |
|
||||
((M0 >> T0) & (0xffffffffll << 32));
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_srlq_M0_T0(void)
|
||||
{
|
||||
M0 >>= T0;
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_sllw_M0_T0(void)
|
||||
{
|
||||
M0 =
|
||||
(((M0 & (0xffffll << 0)) << T0) & (0xffffll << 0)) |
|
||||
(((M0 & (0xffffll << 16)) << T0) & (0xffffll << 16)) |
|
||||
(((M0 & (0xffffll << 32)) << T0) & (0xffffll << 32)) |
|
||||
(((M0 & (0xffffll << 48)) << T0) & (0xffffll << 48));
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
|
||||
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_slll_M0_T0(void)
|
||||
{
|
||||
M0 =
|
||||
((M0 << T0) & (0xffffffffll << 0)) |
|
||||
((M0 & (0xffffffffll << 32)) << T0);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_sllq_M0_T0(void)
|
||||
{
|
||||
M0 <<= T0;
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_sraw_M0_T0(void)
|
||||
{
|
||||
M0 =
|
||||
((uint64_t) ((EXTEND16(M0 >> 0) >> T0) & 0xffff) << 0) |
|
||||
((uint64_t) ((EXTEND16(M0 >> 16) >> T0) & 0xffff) << 16) |
|
||||
((uint64_t) ((EXTEND16(M0 >> 32) >> T0) & 0xffff) << 32) |
|
||||
((uint64_t) ((EXTEND16(M0 >> 48) >> T0) & 0xffff) << 48);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
|
||||
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_sral_M0_T0(void)
|
||||
{
|
||||
M0 =
|
||||
(((EXTEND32(M0 >> 0) >> T0) & 0xffffffff) << 0) |
|
||||
(((EXTEND32(M0 >> 32) >> T0) & 0xffffffff) << 32);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_sraq_M0_T0(void)
|
||||
{
|
||||
M0 = (int64_t) M0 >> T0;
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_rorw_M0_T0(void)
|
||||
{
|
||||
M0 =
|
||||
((((M0 & (0xffffll << 0)) >> T0) |
|
||||
((M0 & (0xffffll << 0)) << (16 - T0))) & (0xffffll << 0)) |
|
||||
((((M0 & (0xffffll << 16)) >> T0) |
|
||||
((M0 & (0xffffll << 16)) << (16 - T0))) & (0xffffll << 16)) |
|
||||
((((M0 & (0xffffll << 32)) >> T0) |
|
||||
((M0 & (0xffffll << 32)) << (16 - T0))) & (0xffffll << 32)) |
|
||||
((((M0 & (0xffffll << 48)) >> T0) |
|
||||
((M0 & (0xffffll << 48)) << (16 - T0))) & (0xffffll << 48));
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
|
||||
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_rorl_M0_T0(void)
|
||||
{
|
||||
M0 =
|
||||
((M0 & (0xffffffffll << 0)) >> T0) |
|
||||
((M0 >> T0) & (0xffffffffll << 32)) |
|
||||
((M0 << (32 - T0)) & (0xffffffffll << 0)) |
|
||||
((M0 & (0xffffffffll << 32)) << (32 - T0));
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_rorq_M0_T0(void)
|
||||
{
|
||||
M0 = (M0 >> T0) | (M0 << (64 - T0));
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_shufh_M0_T0(void)
|
||||
{
|
||||
M0 =
|
||||
(((M0 >> ((T0 << 4) & 0x30)) & 0xffff) << 0) |
|
||||
(((M0 >> ((T0 << 2) & 0x30)) & 0xffff) << 16) |
|
||||
(((M0 >> ((T0 << 0) & 0x30)) & 0xffff) << 32) |
|
||||
(((M0 >> ((T0 >> 2) & 0x30)) & 0xffff) << 48);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
|
||||
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
|
||||
}
|
||||
|
||||
/* TODO: Unsigned-Saturation */
|
||||
void OPPROTO op_iwmmxt_packuw_M0_wRn(void)
|
||||
{
|
||||
M0 =
|
||||
(((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) |
|
||||
(((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) |
|
||||
(((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) |
|
||||
(((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |
|
||||
NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |
|
||||
NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |
|
||||
NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_packul_M0_wRn(void)
|
||||
{
|
||||
M0 =
|
||||
(((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) |
|
||||
(((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
|
||||
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_packuq_M0_wRn(void)
|
||||
{
|
||||
M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
|
||||
}
|
||||
|
||||
/* TODO: Signed-Saturation */
|
||||
void OPPROTO op_iwmmxt_packsw_M0_wRn(void)
|
||||
{
|
||||
M0 =
|
||||
(((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) |
|
||||
(((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) |
|
||||
(((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) |
|
||||
(((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |
|
||||
NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |
|
||||
NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |
|
||||
NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_packsl_M0_wRn(void)
|
||||
{
|
||||
M0 =
|
||||
(((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) |
|
||||
(((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
|
||||
NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_packsq_M0_wRn(void)
|
||||
{
|
||||
M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_muladdsl_M0_T0_T1(void)
|
||||
{
|
||||
M0 += (int32_t) EXTEND32(T0) * (int32_t) EXTEND32(T1);
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_muladdsw_M0_T0_T1(void)
|
||||
{
|
||||
M0 += EXTEND32(EXTEND16S((T0 >> 0) & 0xffff) *
|
||||
EXTEND16S((T1 >> 0) & 0xffff));
|
||||
M0 += EXTEND32(EXTEND16S((T0 >> 16) & 0xffff) *
|
||||
EXTEND16S((T1 >> 16) & 0xffff));
|
||||
}
|
||||
|
||||
void OPPROTO op_iwmmxt_muladdswl_M0_T0_T1(void)
|
||||
{
|
||||
M0 += EXTEND32(EXTEND16S(T0 & 0xffff) *
|
||||
EXTEND16S(T1 & 0xffff));
|
||||
}
|
||||
@ -67,4 +67,24 @@ VFP_MEM_OP(d,q)
|
||||
|
||||
#undef VFP_MEM_OP
|
||||
|
||||
/* iwMMXt load/store. Address is in T1 */
|
||||
#define MMX_MEM_OP(name, ldname) \
|
||||
void OPPROTO glue(op_iwmmxt_ld##name,MEMSUFFIX)(void) \
|
||||
{ \
|
||||
M0 = glue(ld##ldname,MEMSUFFIX)(T1); \
|
||||
FORCE_RET(); \
|
||||
} \
|
||||
void OPPROTO glue(op_iwmmxt_st##name,MEMSUFFIX)(void) \
|
||||
{ \
|
||||
glue(st##name,MEMSUFFIX)(T1, M0); \
|
||||
FORCE_RET(); \
|
||||
}
|
||||
|
||||
MMX_MEM_OP(b, ub)
|
||||
MMX_MEM_OP(w, uw)
|
||||
MMX_MEM_OP(l, l)
|
||||
MMX_MEM_OP(q, q)
|
||||
|
||||
#undef MMX_MEM_OP
|
||||
|
||||
#undef MEMSUFFIX
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -82,6 +82,9 @@ hello-arm: hello-arm.o
|
||||
hello-arm.o: hello-arm.c
|
||||
arm-linux-gcc -Wall -g -O2 -c -o $@ $<
|
||||
|
||||
test-arm-iwmmxt: test-arm-iwmmxt.s
|
||||
cpp < $< | arm-linux-gnu-gcc -Wall -static -march=iwmmxt -mabi=aapcs -x assembler - -o $@
|
||||
|
||||
# MIPS test
|
||||
hello-mips: hello-mips.c
|
||||
mips-linux-gnu-gcc -nostdlib -static -mno-abicalls -fno-PIC -mabi=32 -Wall -Wextra -g -O2 -o $@ $<
|
||||
|
||||
49
tests/test-arm-iwmmxt.s
Normal file
49
tests/test-arm-iwmmxt.s
Normal file
@ -0,0 +1,49 @@
|
||||
@ Checks whether iwMMXt is functional.
|
||||
.code 32
|
||||
.globl main
|
||||
|
||||
main:
|
||||
ldr r0, =data0
|
||||
ldr r1, =data1
|
||||
ldr r2, =data2
|
||||
#ifndef FPA
|
||||
wldrd wr0, [r0, #0]
|
||||
wldrd wr1, [r0, #8]
|
||||
wldrd wr2, [r1, #0]
|
||||
wldrd wr3, [r1, #8]
|
||||
wsubb wr2, wr2, wr0
|
||||
wsubb wr3, wr3, wr1
|
||||
wldrd wr0, [r2, #0]
|
||||
wldrd wr1, [r2, #8]
|
||||
waddb wr0, wr0, wr2
|
||||
waddb wr1, wr1, wr3
|
||||
wstrd wr0, [r2, #0]
|
||||
wstrd wr1, [r2, #8]
|
||||
#else
|
||||
ldfe f0, [r0, #0]
|
||||
ldfe f1, [r0, #8]
|
||||
ldfe f2, [r1, #0]
|
||||
ldfe f3, [r1, #8]
|
||||
adfdp f2, f2, f0
|
||||
adfdp f3, f3, f1
|
||||
ldfe f0, [r2, #0]
|
||||
ldfe f1, [r2, #8]
|
||||
adfd f0, f0, f2
|
||||
adfd f1, f1, f3
|
||||
stfe f0, [r2, #0]
|
||||
stfe f1, [r2, #8]
|
||||
#endif
|
||||
mov r0, #1
|
||||
mov r1, r2
|
||||
mov r2, #0x11
|
||||
swi #0x900004
|
||||
mov r0, #0
|
||||
swi #0x900001
|
||||
|
||||
.data
|
||||
data0:
|
||||
.string "aaaabbbbccccdddd"
|
||||
data1:
|
||||
.string "bbbbccccddddeeee"
|
||||
data2:
|
||||
.string "hvLLWs\x1fsdrs9\x1fNJ-\n"
|
||||
Loading…
x
Reference in New Issue
Block a user