Stanislav Shwartsman
01080243d4
complation fix
2011-12-25 19:58:21 +00:00
Stanislav Shwartsman
a44c1b8e1e
SVM and VMX share tsc offset code
2011-12-25 19:53:23 +00:00
Stanislav Shwartsman
75bda1d5cd
implemented SVM emulation support for Bochs (incomplete yet)
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I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.
Also looking for anybody with existing SVM kernels - as simple as possible - for testing.
Status:
- exceptions intercept is not implemented yet
- IO intercept is not implemented yet
- MSR intercept is not implemented yet
- virtual interrupts are not implemented yet
- CPUID is not implemented yet
No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
e7ed8aca5c
move inhibit interrrupts functionality to icount interface
2011-12-21 06:17:45 +00:00
Stanislav Shwartsman
c28c7f6a06
Supply real VMX capabilities together with the CPU MODEL .bochsrc option.
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So now the same single option will choose not only the CPUID flags but also VMX capabilities matching real HW machine.
Removed cpuid of core2_extreme_x9770 from the cpudb. I don't remember its VMX capabilities anyway.
There is another Penryn model in the cpudb - core2_penryn_t9600.
2011-09-26 12:31:40 +00:00
Stanislav Shwartsman
62d0c8abf7
- Now you could disable x86-64 from .bochsrc so now it is possible to emulate
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32-bit CPU using Bochs binary compiled with x86-64 support.
The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
1b9f286945
- New way of CPUs scheduling in SMP mode brings up to 50% speedup to the
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SMP emulation. New implementation uses dynamic CPU quantum value and takes
full advantage of the trace cache. Each emulated processor will execute
the whole trace before switching to the next processor.
* It is also safe to use large (up to 16 instructions) quantum values for
the SMP emulation now and improve performance even further.
The same merge also completely fixes SF bug :
[3312237] stepN command might be not working properly
Handlers chaining speedups are also supported with SMP emulation now.
2011-09-22 19:38:52 +00:00
Stanislav Shwartsman
96cedbc756
continue handlers-chaining optimization: update time once per trace and not for every instruction
2011-09-06 15:35:39 +00:00
Stanislav Shwartsman
fb9da23f9b
syscall/sysret are not supported outside long64 mode in Intel CPUs
2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
371dc200fc
Remove the 'trace' debug feature fro the main stream (which now runs with handlers chaining) and this way reduce each handler size.
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Another 3% speedup on WinXP boot on top of handlers chaining + reduction of Bochs binary size by 45K.
2011-08-21 17:04:21 +00:00
Stanislav Shwartsman
4a3209ae31
Increase cpu param length (exceeded with new icount variable)
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CHECK_MAX_INSTRUCTIONS is not needed for debugger anymore.
Next step: eliminate it for SMP as well and remove cpu_loop parameter.
2011-08-17 20:00:51 +00:00
Stanislav Shwartsman
b69f728246
Fixed internal debugger part of the bug:
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#3312237 stepN command might be not working properly
The problem still can be exists for SMP.
2011-08-17 19:51:32 +00:00
Stanislav Shwartsman
6606c62439
cr4 available since Pentium only
2011-08-16 16:49:04 +00:00
Stanislav Shwartsman
8962cfddde
re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc
2011-08-12 18:04:56 +00:00
Stanislav Shwartsman
7af5dccdcf
fixed compilation issue
2011-08-11 19:45:21 +00:00
Stanislav Shwartsman
f15bc6cf75
support for NX outside of x86-64.
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required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
1b27438146
cleanups + small code reorg
2011-08-10 20:31:29 +00:00
Stanislav Shwartsman
2ee0029749
extract ffxsr support to separate CPU feature
2011-08-04 19:02:49 +00:00
Stanislav Shwartsman
1d89709e62
Added another CPU to CPUDB: p4_willamette (one more without x86-64 support).
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Reimplemented CPUDB using pure C macros magic.
Fixed compilation errors when compiling with SMP on.
2011-07-31 18:43:46 +00:00
Stanislav Shwartsman
6e6db04b8f
Fixed compilation errors, dos2unix, added missed p3_katmai.txt
2011-07-31 14:56:45 +00:00
Stanislav Shwartsman
5e291e0860
Added Athlon64 Clawhammer CPUID to CPUDB
2011-07-30 21:28:16 +00:00
Stanislav Shwartsman
fefa4d5e5b
added PIII Katmai to CPUDB
2011-07-30 14:30:35 +00:00
Stanislav Shwartsman
4ac67ec386
compilation when cu_level < 4
2011-07-29 15:24:32 +00:00
Stanislav Shwartsman
1a051f9f00
Added several predefined CPUs that can be selected from .bochsrc using new CPU::MODEL option.
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Selecting CPU MODEL from .bochsrc automatically chooses real HW CPUID and also configures Bochs emulator to emulate this specific CPU including all its features only.
Supported CPUs to choose from:
core2_extreme_x9770
corei7_sandy_bridge_2600K
p4_prescott_celeron_336
2011-07-29 15:03:54 +00:00
Stanislav Shwartsman
78327d3e5e
First step toward completely configurable CPU.
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Change CPUID to generic interface which could be chosen from .bochsrc.
Bochs CPU emulation will enable/disable features (like instruction sets) according to CPUID that is selected.
TODO: Add database of CPUID from real hardware CPUs
2011-07-28 16:17:42 +00:00
Stanislav Shwartsman
81f6a283e2
trim cpuid info from save/restore tree
2011-07-27 14:16:51 +00:00
Stanislav Shwartsman
cddd1e3758
MONITOR/MWAIT: Do monitor on cache line granularity only + bugfix with possible TLB caching of monitored line
2011-07-18 21:44:22 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
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Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
909e750549
Implemented VMX preemption timer VMEXIT control (patch by Jianan Hao)
2011-07-03 15:59:48 +00:00
Stanislav Shwartsman
beafa7c88b
improved x86 hw code bp handling
2011-06-24 13:38:34 +00:00
Stanislav Shwartsman
024a1ace38
move X2APIC to be .bochsrc option, rework of the cpuid code
2011-04-21 13:27:42 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
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many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
63fe52f601
accessors for DR6 and DR7 fields
2011-03-15 20:20:15 +00:00
Stanislav Shwartsman
aff763349d
Fixed save/restore of segments in real mode (valid bit was corrupted)
2011-03-12 09:56:43 +00:00
Stanislav Shwartsman
93e152ef1a
no need to read ignore_bad_msrs on every reset
2011-03-05 18:54:23 +00:00
Stanislav Shwartsman
3b8903e19d
there is no need to duplicate ignore_bad_msrs in param tree, this knob is loaded from options anyway
2011-03-05 18:47:48 +00:00
Stanislav Shwartsman
2d1d41e731
CPUID is not available when cpu-level=3
2011-02-25 16:27:01 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
43600f3756
complete rework of SSE code
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next step - split all SSE opcodes by ModC0
2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
c7017b1c05
simplification
2010-12-19 21:41:15 +00:00
Stanislav Shwartsman
4a85a8680e
SSE optimization
2010-12-19 07:06:40 +00:00
Stanislav Shwartsman
1047acb2cc
rename SSE register param - prepare for wide SSE register (AVX)
2010-12-06 21:52:41 +00:00
Stanislav Shwartsman
eaa2e0e0ea
[PATCH] cpu/init.cc: proper CPL restore in after_restore_statE
2010-06-04 20:31:04 +00:00
Stanislav Shwartsman
b2dffd9258
undo incorrect change for ia32_feature_control msr init
2010-05-23 05:32:00 +00:00
Stanislav Shwartsman
b6c26d394c
enable VMX lock bit - required for VMXON
2010-05-22 10:21:31 +00:00
Stanislav Shwartsman
0478b326c3
remove ome ifdefs
2010-05-02 15:11:39 +00:00
Stanislav Shwartsman
b9be4fcd3e
fix
2010-04-19 11:09:35 +00:00
Stanislav Shwartsman
b85791686b
fixed mtrr_deftype reset value
2010-04-10 07:32:48 +00:00
Stanislav Shwartsman
04349e1041
compilation fix for CPU < 6
2010-04-09 07:15:54 +00:00
Stanislav Shwartsman
6e1204cb84
Merged X2APIC + X2APIC virtualization
2010-04-08 15:50:39 +00:00
Stanislav Shwartsman
10505dca81
PDPTR checks fix
2010-04-06 19:26:03 +00:00
Stanislav Shwartsman
21de4f8b8b
remove cr3_masked
2010-04-04 09:04:12 +00:00
Stanislav Shwartsman
d39d485ece
changes variable name to better one
2010-04-03 05:59:07 +00:00
Stanislav Shwartsman
a220edc5bb
compile fixes
2010-03-26 11:09:12 +00:00
Stanislav Shwartsman
64e9ff6aff
add PDPTRS into param tree
2010-03-25 22:04:31 +00:00
Stanislav Shwartsman
f5ce2a7639
split crreg access functions to separate file
2010-03-25 21:33:07 +00:00
Stanislav Shwartsman
79466dffe2
apic virtualization + vmx fixes
2010-03-16 14:51:20 +00:00
Stanislav Shwartsman
5d2c2879a7
IA32_FEATURE_CONTROL_MSR is implemented
2010-03-06 16:59:05 +00:00
Stanislav Shwartsman
189553d702
bugfix
2010-03-05 08:54:07 +00:00
Stanislav Shwartsman
01cfbdccbc
Move MMX to be runtime option
2010-03-01 18:53:53 +00:00
Stanislav Shwartsman
5b6a14656d
Make XSAVE as runtime option
2010-02-26 22:53:43 +00:00
Stanislav Shwartsman
5df864b1f1
Move param_names.h into bochs root folder
2010-02-26 14:18:19 +00:00
Stanislav Shwartsman
927c3594d6
enable compilation with CPU_LEVEL <= 6
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converted SEP to runtime option as well
2010-02-26 11:44:50 +00:00
Stanislav Shwartsman
78a420faa1
first updates
2010-02-25 22:34:56 +00:00
Stanislav Shwartsman
033a20b3b2
allow to configure CPU features at runtime - implemened on example of SSE/AES/MOVBE/POPCNT
2010-02-25 22:04:31 +00:00
Stanislav Shwartsman
bd60e0264c
change Copyright to Bochs Project
2009-12-04 16:53:12 +00:00
Stanislav Shwartsman
0a735942e2
restore real mode with CPL != 0
2009-11-20 14:18:43 +00:00
Stanislav Shwartsman
5099cff0e5
save restore for new var
2009-11-13 16:01:37 +00:00
Stanislav Shwartsman
71bb10f98c
move ignore-bad-msrs to runtime option in ,bochsrc
2009-11-13 15:55:46 +00:00
Stanislav Shwartsman
6f0db17b08
fixed #DB on rpeat instructions
2009-10-30 09:13:19 +00:00
Stanislav Shwartsman
da4722e257
optimize sr params
2009-10-16 18:29:45 +00:00
Stanislav Shwartsman
d26660dac1
small fixes
2009-08-19 09:59:30 +00:00
Stanislav Shwartsman
d44dc8b83c
Fix param name
2009-07-28 14:52:19 +00:00
Stanislav Shwartsman
66c4654418
segment desriptor 'A' bit handling fixes
2009-07-27 05:52:28 +00:00
Stanislav Shwartsman
733491871d
copy/paste typo fix
2009-06-15 15:10:05 +00:00
Stanislav Shwartsman
cd445195dd
cleanup configure options. All paging related stuff is now automatically set/unset according to cpu-level option.
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Related configure options (--enable-pae, --enable-mtrr, --enable-global-pages, --enable-large-pages) are deprecated.
Less configure options - less configure problems :)
2009-06-15 09:30:56 +00:00
Stanislav Shwartsman
3d7bbf4356
fixed VMXON pointer concept
2009-05-28 08:26:17 +00:00
Stanislav Shwartsman
847179fd13
mtrr reverved bits check
2009-05-21 13:25:30 +00:00
Stanislav Shwartsman
aac70fdf25
faster vmenter/vmexit
2009-05-03 13:02:14 +00:00
Stanislav Shwartsman
78418c6a74
removed cr1 from cpu
2009-05-01 09:32:46 +00:00
Stanislav Shwartsman
153f86b1a8
save/restore mwait status correctly
2009-04-05 19:38:44 +00:00
Stanislav Shwartsman
9e092a86c3
merge "system" and "segment" blocks of descriptor
2009-04-05 19:09:44 +00:00
Stanislav Shwartsman
c9383813f0
don't have to keep both limit and limit_scale
2009-04-05 18:16:29 +00:00
Stanislav Shwartsman
a0b1fda178
bugfixes
2009-03-27 16:42:21 +00:00
Stanislav Shwartsman
4470c6a1c8
make ICACHE always enabled option and deprecate it in the configure script
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Trace cache still can be turned off
2009-03-13 18:48:08 +00:00
Stanislav Shwartsman
09489f968a
cleanup APIC initialization and setting of APIC_ID
2009-02-20 17:26:01 +00:00
Stanislav Shwartsman
78590cc6f2
remove redundant cpu->name variable
2009-02-20 17:05:03 +00:00
Stanislav Shwartsman
7be90a7426
forgot to enable local_apic in init()
2009-02-18 22:38:58 +00:00
Stanislav Shwartsman
3564ef3162
small fixes
2009-02-18 22:33:06 +00:00
Stanislav Shwartsman
3a1852ea23
take local APIC read/write access into CPU class from BX_MEM (needed for APIC virtualization later)
2009-02-17 19:20:47 +00:00
Stanislav Shwartsman
fdf4f25230
revert incorret merge
2009-02-03 19:28:22 +00:00
Stanislav Shwartsman
fbc6f04d8a
correctly deliver INIT
2009-02-03 19:26:09 +00:00
Stanislav Shwartsman
592484408f
Initial NMI virtualization for VMX, clean out CPU pins set/clear code
2009-02-03 19:17:15 +00:00
Stanislav Shwartsman
9430c5cf95
INIT pin is blocked when CPU is waiting for SIPI
2009-01-31 11:53:57 +00:00
Stanislav Shwartsman
f8185a6bc6
Added Intel VMX emulation to Bochs CPU
2009-01-31 10:43:24 +00:00
Stanislav Shwartsman
a1c11c788b
sepatate activity state from debug trap
2009-01-29 20:27:57 +00:00
Stanislav Shwartsman
cd90782293
No need to save/restore EXT field
2009-01-23 17:48:38 +00:00
Stanislav Shwartsman
a396c8a1ce
Rework SMM mess
2009-01-17 22:35:45 +00:00
Volker Ruppert
501952efdd
- removed unused logfunctions member 'type' and related method 'settype()'
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- updated FSF address in copyright
2009-01-10 11:30:20 +00:00
Stanislav Shwartsman
836e9649d8
modify set cr0 functionality
2009-01-10 10:07:57 +00:00
