Move MMX to be runtime option
This commit is contained in:
Stanislav Shwartsman
parent
160d4bbded
commit
01cfbdccbc
@ -142,6 +142,10 @@ cpu: count=1, ips=50000000, reset_on_triple_fault=1, ignore_bad_msrs=1, msrs="ms
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#
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# This defines features and functionality supported by Bochs emulated CPU:
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#
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# MMX:
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# Select MMX instruction set support.
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# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 5.
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#
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# SEP:
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# Select SYSENTER/SYSEXIT instruction set support.
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# This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
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@ -179,7 +183,7 @@ cpu: count=1, ips=50000000, reset_on_triple_fault=1, ignore_bad_msrs=1, msrs="ms
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# Determine whether to limit maximum CPUID function to 3. This mode is
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# required to workaround WinNT installation and boot issues.
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#=======================================================================
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cpuid: sep=1, sse=sse4_2, xapic=1, aes=1, movbe=1, xsave=1, cpuid_limit_winnt=0
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cpuid: mmx=1, sep=1, sse=sse4_2, xapic=1, aes=1, movbe=1, xsave=1, cpuid_limit_winnt=0
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#=======================================================================
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# MEMORY
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@ -12,7 +12,6 @@
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--enable-debugger \
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--enable-disasm \
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--enable-debugger-gui \
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--enable-mmx \
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--enable-fpu \
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--enable-misaligned-sse \
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--enable-alignment-check \
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@ -21,7 +21,8 @@ Detailed change log :
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Now you could enable/disable any of SSEx/AES/MOVBE/SYSENTER_SYSEXIT/XSAVE
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instruction sets using new CPUID option in .bochsrc.
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Configure options:
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--enable-sse, --enable-aes, --enable-movbe, --enable-sep, --enable-xsave
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--enable-mmx, --enable-sse, --enable-movbe, --enable-xsave,
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--enable-sep, --enable-aes
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are deprecated and should not be used anymore.
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- Local APIC configure option --enable-apic is deprecated and should not
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@ -49,6 +50,9 @@ Detailed change log :
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- I/O Devices
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- USB HP DeskJet 920C printer device emulation (Ben Lunt)
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- Misc
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- Updated Bochs TESTFORM to version 0.5
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- SF patches applied
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[2938273] allow instrumentation to change execute by Konrad Grochowski
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[2926072] Indirection operators in expressions by Derek Peschel
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@ -1,4 +1,4 @@
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$Id: PARAM_TREE.txt,v 1.26 2010-02-28 14:52:16 sshwarts Exp $
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$Id: PARAM_TREE.txt,v 1.27 2010-03-01 18:53:53 sshwarts Exp $
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Starting from Bochs 2.3 the parameters are organized in a tree structure
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instead of a huge flat list. The parameter tree was required for implementing
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@ -29,6 +29,7 @@ cpuid
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cpuid_limit_winnt
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vendor_string
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brand_string
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mmx
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sep
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sse
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aes
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dbg_main.cc,v 1.232 2010-02-26 14:18:18 sshwarts Exp $
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// $Id: dbg_main.cc,v 1.233 2010-03-01 18:53:53 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2009 The Bochs Project
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@ -706,16 +706,22 @@ void bx_dbg_print_sse_state(void)
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void bx_dbg_print_mmx_state(void)
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{
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#if BX_SUPPORT_MMX
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char param_name[20];
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for(unsigned i=0;i<8;i++) {
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sprintf(param_name, "FPU.st%d.fraction", i);
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Bit64u mmreg = SIM->get_param_num(param_name, dbg_cpu_list)->get64();
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dbg_printf("MM[%d]: %08x:%08x\n", i, GET32H(mmreg), GET32L(mmreg));
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#if BX_CPU_LEVEL >= 5
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Bit32u cpuid_features_bitmask = SIM->get_param_num("cpuid_features_bitmask", dbg_cpu_list)->get();
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if ((cpuid_features_bitmask & BX_CPU_MMX) != 0) {
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char param_name[20];
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for(unsigned i=0;i<8;i++) {
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sprintf(param_name, "FPU.st%d.fraction", i);
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Bit64u mmreg = SIM->get_param_num(param_name, dbg_cpu_list)->get64();
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dbg_printf("MM[%d]: %08x:%08x\n", i, GET32H(mmreg), GET32L(mmreg));
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}
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}
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#else
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dbg_printf("The CPU doesn't support MMX state !\n");
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else
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#endif
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{
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dbg_printf("The CPU doesn't support MMX state !\n");
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}
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}
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void bx_dbg_print_fpu_state(void)
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: config.cc,v 1.198 2010-02-28 14:52:16 sshwarts Exp $
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// $Id: config.cc,v 1.199 2010-03-01 18:53:53 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002-2009 The Bochs Project
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@ -358,7 +358,7 @@ void bx_init_options()
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cpu_param->set_options(menu->SHOW_PARENT);
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// cpuid subtree
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bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 9);
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bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 10);
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new bx_param_bool_c(cpuid_param,
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"cpuid_limit_winnt", "Limit max CPUID function to 3",
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@ -386,6 +386,13 @@ void bx_init_options()
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#endif
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BX_CPUID_BRAND_LEN+1);
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#if BX_CPU_LEVEL >= 5
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new bx_param_bool_c(cpuid_param,
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"mmx", "Support for MMX instruction set",
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"Support for MMX instruction set",
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1);
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#endif
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#if BX_CPU_LEVEL >= 6
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// configure defaults to CPU_LEVEL = 6 with SSE2 enabled
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static const char *sse_names[] = { "none", "sse", "sse2", "sse3", "ssse3", "sse4_1", "sse4_2", NULL };
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@ -2173,6 +2180,16 @@ static int parse_debug_symbols(const char *context, const char **params, int num
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return 0;
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}
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static int parse_param_bool(const char *input, int len, const char *param)
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{
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if (input[len] == '0' || input[len] == '1') {
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SIM->get_param_bool(param)->set(input[len] - '0');
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return 0;
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}
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return -1;
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}
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static int parse_line_formatted(const char *context, int num_params, char *params[])
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{
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int i, slot, t;
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@ -2482,11 +2499,7 @@ static int parse_line_formatted(const char *context, int num_params, char *param
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if (strncmp(params[1], "disabled=", 9)) {
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PARSE_ERR(("%s: floppy_bootsig_check directive malformed.", context));
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}
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if (params[1][9] == '0')
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SIM->get_param_bool(BXPN_FLOPPYSIGCHECK)->set(0);
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else if (params[1][9] == '1')
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SIM->get_param_bool(BXPN_FLOPPYSIGCHECK)->set(1);
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else {
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if (parse_param_bool(params[1], 9, BXPN_FLOPPYSIGCHECK) < 0) {
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PARSE_ERR(("%s: floppy_bootsig_check directive malformed.", context));
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}
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} else if (!strcmp(params[0], "log")) {
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@ -2561,16 +2574,12 @@ static int parse_line_formatted(const char *context, int num_params, char *param
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SIM->get_param_num(BXPN_SMP_QUANTUM)->set(atol(¶ms[i][8]));
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#endif
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} else if (!strncmp(params[i], "reset_on_triple_fault=", 22)) {
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if (params[i][22] == '0' || params[i][22] == '1') {
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SIM->get_param_bool(BXPN_RESET_ON_TRIPLE_FAULT)->set(params[i][22] - '0');
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} else {
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if (parse_param_bool(params[i], 22, BXPN_RESET_ON_TRIPLE_FAULT) < 0) {
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PARSE_ERR(("%s: cpu directive malformed.", context));
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}
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#if BX_CPU_LEVEL >= 5
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} else if (!strncmp(params[i], "ignore_bad_msrs=", 16)) {
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if (params[i][16] == '0' || params[i][16] == '1') {
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SIM->get_param_bool(BXPN_IGNORE_BAD_MSRS)->set(params[i][16] - '0');
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} else {
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if (parse_param_bool(params[i], 16, BXPN_IGNORE_BAD_MSRS) < 0) {
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PARSE_ERR(("%s: cpu directive malformed.", context));
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}
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#endif
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@ -2596,43 +2605,37 @@ static int parse_line_formatted(const char *context, int num_params, char *param
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}
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SIM->get_param_string(BXPN_BRAND_STRING)->set(¶ms[i][13]);
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} else if (!strncmp(params[i], "cpuid_limit_winnt=", 18)) {
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if (params[i][18] == '0' || params[i][18] == '1') {
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SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->set(params[i][18] - '0');
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} else {
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if (parse_param_bool(params[i], 18, BXPN_CPUID_LIMIT_WINNT) < 0) {
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PARSE_ERR(("%s: cpuid directive malformed.", context));
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}
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#if BX_CPU_LEVEL >= 5
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} else if (!strncmp(params[i], "mmx=", 4)) {
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if (parse_param_bool(params[i], 4, BXPN_CPUID_MMX) < 0) {
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PARSE_ERR(("%s: cpuid directive malformed.", context));
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}
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#endif
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#if BX_CPU_LEVEL >= 6
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} else if (!strncmp(params[i], "sse=", 4)) {
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if (! SIM->get_param_enum(BXPN_CPUID_SSE)->set_by_name(¶ms[i][4]))
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PARSE_ERR(("%s: unsupported sse option.", context));
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} else if (!strncmp(params[i], "aes=", 4)) {
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if (params[i][4] == '0' || params[i][4] == '1') {
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SIM->get_param_bool(BXPN_CPUID_AES)->set(params[i][4] - '0');
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} else {
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if (parse_param_bool(params[i], 4, BXPN_CPUID_AES) < 0) {
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PARSE_ERR(("%s: cpuid directive malformed.", context));
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}
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} else if (!strncmp(params[i], "movbe=", 6)) {
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if (params[i][6] == '0' || params[i][6] == '1') {
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SIM->get_param_bool(BXPN_CPUID_MOVBE)->set(params[i][6] - '0');
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} else {
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if (parse_param_bool(params[i], 6, BXPN_CPUID_MOVBE) < 0) {
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PARSE_ERR(("%s: cpuid directive malformed.", context));
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}
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} else if (!strncmp(params[i], "sep=", 4)) {
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if (params[i][4] == '0' || params[i][4] == '1') {
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SIM->get_param_bool(BXPN_CPUID_SEP)->set(params[i][4] - '0');
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} else {
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if (parse_param_bool(params[i], 4, BXPN_CPUID_SEP) < 0) {
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PARSE_ERR(("%s: cpuid directive malformed.", context));
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}
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} else if (!strncmp(params[i], "xsave=", 6)) {
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if (params[i][6] == '0' || params[i][6] == '1') {
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SIM->get_param_bool(BXPN_CPUID_XSAVE)->set(params[i][6] - '0');
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} else {
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if (parse_param_bool(params[i], 6, BXPN_CPUID_XSAVE) < 0) {
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PARSE_ERR(("%s: cpuid directive malformed.", context));
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}
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} else if (!strncmp(params[i], "xapic=", 6)) {
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if (params[i][6] == '0' || params[i][6] == '1') {
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SIM->get_param_bool(BXPN_CPUID_XAPIC)->set(params[i][6] - '0');
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} else {
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if (parse_param_bool(params[i], 6, BXPN_CPUID_XAPIC) < 0) {
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PARSE_ERR(("%s: cpuid directive malformed.", context));
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}
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#endif
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@ -2768,10 +2771,9 @@ static int parse_line_formatted(const char *context, int num_params, char *param
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PARSE_ERR(("%s: text_snapshot_check directive: wrong # args.", context));
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}
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if (!strncmp(params[1], "enabled=", 8)) {
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if (params[1][8] == '0' || params[1][8] == '1')
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SIM->get_param_bool(BXPN_TEXT_SNAPSHOT_CHECK)->set(params[1][8] - '0');
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else
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if (parse_param_bool(params[1], 8, BXPN_TEXT_SNAPSHOT_CHECK) < 0) {
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PARSE_ERR(("%s: text_snapshot_check directive malformed.", context));
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}
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} else {
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PARSE_ERR(("%s: text_snapshot_check directive malformed.", context));
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}
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@ -2781,10 +2783,9 @@ static int parse_line_formatted(const char *context, int num_params, char *param
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}
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for (i=1; i<num_params; i++) {
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if (!strncmp(params[i], "enabled=", 8)) {
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if (params[i][8] == '0' || params[i][8] == '1')
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SIM->get_param_bool(BXPN_MOUSE_ENABLED)->set(params[i][8] - '0');
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else
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if (parse_param_bool(params[1], 8, BXPN_MOUSE_ENABLED) < 0) {
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PARSE_ERR(("%s: mouse directive malformed.", context));
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}
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} else if (!strncmp(params[i], "type=", 5)) {
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if (!SIM->get_param_enum(BXPN_MOUSE_TYPE)->set_by_name(¶ms[i][5]))
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PARSE_ERR(("%s: mouse type '%s' not available", context, ¶ms[i][5]));
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@ -2799,9 +2800,7 @@ static int parse_line_formatted(const char *context, int num_params, char *param
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if (strncmp(params[1], "enabled=", 8)) {
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PARSE_ERR(("%s: private_colormap directive malformed.", context));
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}
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if (params[1][8] == '0' || params[1][8] == '1')
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SIM->get_param_bool(BXPN_PRIVATE_COLORMAP)->set(params[1][8] - '0');
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else {
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if (parse_param_bool(params[1], 8, BXPN_PRIVATE_COLORMAP) < 0) {
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PARSE_ERR(("%s: private_colormap directive malformed.", context));
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}
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} else if (!strcmp(params[0], "fullscreen")) {
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@ -2812,9 +2811,7 @@ static int parse_line_formatted(const char *context, int num_params, char *param
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if (strncmp(params[1], "enabled=", 8)) {
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PARSE_ERR(("%s: fullscreen directive malformed.", context));
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}
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if (params[1][8] == '0' || params[1][8] == '1') {
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SIM->get_param_bool(BXPN_FULLSCREEN)->set(params[1][8] - '0');
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} else {
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if (parse_param_bool(params[1], 8, BXPN_FULLSCREEN) < 0) {
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PARSE_ERR(("%s: fullscreen directive malformed.", context));
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}
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#endif
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@ -3094,10 +3091,7 @@ static int parse_line_formatted(const char *context, int num_params, char *param
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if (strncmp(params[1], "enabled=", 8)) {
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PARSE_ERR(("%s: port_e9_hack directive malformed.", context));
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}
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if (params[1][8] == '0' || params[1][8] == '1') {
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SIM->get_param_bool(BXPN_PORT_E9_HACK)->set(atoi(¶ms[1][8]));
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}
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else {
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if (parse_param_bool(params[1], 8, BXPN_PORT_E9_HACK) < 0) {
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PARSE_ERR(("%s: port_e9_hack directive malformed.", context));
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}
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}
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@ -3796,6 +3790,9 @@ int bx_write_configuration(const char *rc, int overwrite)
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#endif
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fprintf(fp, "\n");
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fprintf(fp, "cpuid: cpuid_limit_winnt=%d", SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get());
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#if BX_CPU_LEVEL >= 5
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fprintf(fp, ", mmx=%d", SIM->get_param_bool(BXPN_CPUID_MMX)->get());
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#endif
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#if BX_CPU_LEVEL >= 6
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fprintf(fp, ", sse=%s, xapic=%d, sep=%d, aes=%d, xsave=%d, movbe=%d",
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SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected(),
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@ -683,7 +683,6 @@ typedef
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#define BX_SUPPORT_ALIGNMENT_CHECK 0
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#define BX_SUPPORT_FPU 0
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#define BX_SUPPORT_MMX 0
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#define BX_SUPPORT_3DNOW 0
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#define BX_SUPPORT_MISALIGNED_SSE 0
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#define BX_SUPPORT_MONITOR_MWAIT 0
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@ -715,26 +714,14 @@ typedef
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#error MSRs are supported only with CPU level >= 5 !
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#endif
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#if (BX_SUPPORT_MMX && BX_CPU_LEVEL < 5)
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#error With CPU level < 5, you must disable MMX support !
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#endif
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#if (!BX_SUPPORT_FPU && BX_CPU_LEVEL > 4)
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#error With CPU level > 4, you must enable FPU support !
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#endif
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#if (BX_SUPPORT_MMX && !BX_SUPPORT_FPU)
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#error "MMX cannot be compiled without FPU support !"
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#endif
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#if (BX_SUPPORT_FPU && BX_CPU_LEVEL < 3)
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#error "FPU cannot be compiled without cpu level >= 3 !"
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#endif
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#if (BX_SUPPORT_3DNOW && !BX_SUPPORT_MMX)
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#error "3DNow! cannot be compiled without MMX support !"
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#endif
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#if (BX_CPU_LEVEL<6 && BX_SUPPORT_VMX)
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#error "VMX only supported with CPU_LEVEL >= 6 !"
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#endif
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98
bochs/configure
vendored
98
bochs/configure
vendored
@ -1,5 +1,5 @@
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#! /bin/sh
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# From configure.in Id: configure.in,v 1.427 2010/02/26 22:53:43 sshwarts Exp .
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# From configure.in Id: configure.in,v 1.428 2010/02/28 14:52:16 sshwarts Exp .
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# Guess values for system-dependent variables and create Makefiles.
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# Generated by GNU Autoconf 2.65.
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#
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@ -972,7 +972,6 @@ enable_vbe
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enable_clgd54xx
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enable_fpu
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enable_vmx
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enable_mmx
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enable_3dnow
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enable_alignment_check
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enable_misaligned_sse
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@ -1690,7 +1689,6 @@ Optional Features:
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--enable-clgd54xx enable CLGD54XX emulation
|
||||
--enable-fpu compile in FPU emulation
|
||||
--enable-vmx virtualization extensions
|
||||
--enable-mmx MMX support
|
||||
--enable-3dnow 3DNow! support (incomplete)
|
||||
--enable-alignment-check alignment check (#AC) support
|
||||
--enable-misaligned-sse misaligned SSE support
|
||||
@ -5099,7 +5097,7 @@ ia64-*-hpux*)
|
||||
;;
|
||||
*-*-irix6*)
|
||||
# Find out which ABI we are using.
|
||||
echo '#line 5102 "configure"' > conftest.$ac_ext
|
||||
echo '#line 5100 "configure"' > conftest.$ac_ext
|
||||
if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5
|
||||
(eval $ac_compile) 2>&5
|
||||
ac_status=$?
|
||||
@ -6788,11 +6786,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:6791: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:6789: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>conftest.err)
|
||||
ac_status=$?
|
||||
cat conftest.err >&5
|
||||
echo "$as_me:6795: \$? = $ac_status" >&5
|
||||
echo "$as_me:6793: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s "$ac_outfile"; then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
# So say no if there are warnings
|
||||
@ -7021,11 +7019,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:7024: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:7022: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>conftest.err)
|
||||
ac_status=$?
|
||||
cat conftest.err >&5
|
||||
echo "$as_me:7028: \$? = $ac_status" >&5
|
||||
echo "$as_me:7026: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s "$ac_outfile"; then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
# So say no if there are warnings
|
||||
@ -7088,11 +7086,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:7091: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:7089: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>out/conftest.err)
|
||||
ac_status=$?
|
||||
cat out/conftest.err >&5
|
||||
echo "$as_me:7095: \$? = $ac_status" >&5
|
||||
echo "$as_me:7093: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s out/conftest2.$ac_objext
|
||||
then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
@ -8878,7 +8876,7 @@ else
|
||||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 8881 "configure"
|
||||
#line 8879 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
@ -8976,7 +8974,7 @@ else
|
||||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 8979 "configure"
|
||||
#line 8977 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
@ -11091,11 +11089,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:11094: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:11092: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>conftest.err)
|
||||
ac_status=$?
|
||||
cat conftest.err >&5
|
||||
echo "$as_me:11098: \$? = $ac_status" >&5
|
||||
echo "$as_me:11096: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s "$ac_outfile"; then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
# So say no if there are warnings
|
||||
@ -11158,11 +11156,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:11161: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:11159: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>out/conftest.err)
|
||||
ac_status=$?
|
||||
cat out/conftest.err >&5
|
||||
echo "$as_me:11165: \$? = $ac_status" >&5
|
||||
echo "$as_me:11163: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s out/conftest2.$ac_objext
|
||||
then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
@ -12183,7 +12181,7 @@ else
|
||||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 12186 "configure"
|
||||
#line 12184 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
@ -12281,7 +12279,7 @@ else
|
||||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 12284 "configure"
|
||||
#line 12282 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
@ -13104,11 +13102,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:13107: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:13105: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>conftest.err)
|
||||
ac_status=$?
|
||||
cat conftest.err >&5
|
||||
echo "$as_me:13111: \$? = $ac_status" >&5
|
||||
echo "$as_me:13109: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s "$ac_outfile"; then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
# So say no if there are warnings
|
||||
@ -13171,11 +13169,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:13174: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:13172: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>out/conftest.err)
|
||||
ac_status=$?
|
||||
cat out/conftest.err >&5
|
||||
echo "$as_me:13178: \$? = $ac_status" >&5
|
||||
echo "$as_me:13176: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s out/conftest2.$ac_objext
|
||||
then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
@ -15136,11 +15134,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:15139: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:15137: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>conftest.err)
|
||||
ac_status=$?
|
||||
cat conftest.err >&5
|
||||
echo "$as_me:15143: \$? = $ac_status" >&5
|
||||
echo "$as_me:15141: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s "$ac_outfile"; then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
# So say no if there are warnings
|
||||
@ -15369,11 +15367,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:15372: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:15370: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>conftest.err)
|
||||
ac_status=$?
|
||||
cat conftest.err >&5
|
||||
echo "$as_me:15376: \$? = $ac_status" >&5
|
||||
echo "$as_me:15374: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s "$ac_outfile"; then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
# So say no if there are warnings
|
||||
@ -15436,11 +15434,11 @@ else
|
||||
-e 's:.*FLAGS}? :&$lt_compiler_flag :; t' \
|
||||
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
|
||||
-e 's:$: $lt_compiler_flag:'`
|
||||
(eval echo "\"\$as_me:15439: $lt_compile\"" >&5)
|
||||
(eval echo "\"\$as_me:15437: $lt_compile\"" >&5)
|
||||
(eval "$lt_compile" 2>out/conftest.err)
|
||||
ac_status=$?
|
||||
cat out/conftest.err >&5
|
||||
echo "$as_me:15443: \$? = $ac_status" >&5
|
||||
echo "$as_me:15441: \$? = $ac_status" >&5
|
||||
if (exit $ac_status) && test -s out/conftest2.$ac_objext
|
||||
then
|
||||
# The compiler can only warn and ignore the option if not recognized
|
||||
@ -17226,7 +17224,7 @@ else
|
||||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 17229 "configure"
|
||||
#line 17227 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
@ -17324,7 +17322,7 @@ else
|
||||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 17327 "configure"
|
||||
#line 17325 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
@ -19011,7 +19009,7 @@ else
|
||||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<EOF
|
||||
#line 19014 "configure"
|
||||
#line 19012 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
@ -21765,6 +21763,10 @@ $as_echo "6" >&6; }
|
||||
echo "ERROR: with >1 processor, use --enable-cpu-level=6"
|
||||
exit 1
|
||||
fi
|
||||
if test "$use_x86_64" = 1 -a "$enableval" -lt 6; then
|
||||
echo "ERROR: --enable-cpu-level=6 required for x86-64 emulation"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
else
|
||||
|
||||
@ -23020,40 +23022,6 @@ if test "$support_vmx" -lt 0 -a "$bx_cpu_level" -lt 6; then
|
||||
as_fn_error "for VMX support the CPU level must be set to 6" "$LINENO" 5
|
||||
fi
|
||||
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for MMX support" >&5
|
||||
$as_echo_n "checking for MMX support... " >&6; }
|
||||
# Check whether --enable-mmx was given.
|
||||
if test "${enable_mmx+set}" = set; then :
|
||||
enableval=$enable_mmx; if test "$enableval" = yes; then
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
|
||||
$as_echo "yes" >&6; }
|
||||
$as_echo "#define BX_SUPPORT_MMX 1" >>confdefs.h
|
||||
|
||||
elif test "$enableval" = no; then
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
|
||||
$as_echo "no" >&6; }
|
||||
$as_echo "#define BX_SUPPORT_MMX 0" >>confdefs.h
|
||||
|
||||
fi
|
||||
|
||||
else
|
||||
|
||||
if test "$bx_cpu_level" -ge 5; then
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
|
||||
$as_echo "yes" >&6; }
|
||||
$as_echo "#define BX_SUPPORT_MMX 1" >>confdefs.h
|
||||
|
||||
else
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
|
||||
$as_echo "no" >&6; }
|
||||
$as_echo "#define BX_SUPPORT_MMX 0" >>confdefs.h
|
||||
|
||||
fi
|
||||
|
||||
|
||||
fi
|
||||
|
||||
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for 3DNow! support" >&5
|
||||
$as_echo_n "checking for 3DNow! support... " >&6; }
|
||||
# Check whether --enable-3dnow was given.
|
||||
|
||||
@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script.
|
||||
|
||||
AC_PREREQ(2.50)
|
||||
AC_INIT(bochs.h)
|
||||
AC_REVISION([[$Id: configure.in,v 1.428 2010-02-28 14:52:16 sshwarts Exp $]])
|
||||
AC_REVISION([[$Id: configure.in,v 1.429 2010-03-01 18:53:53 sshwarts Exp $]])
|
||||
AC_CONFIG_HEADER(config.h)
|
||||
AC_CONFIG_HEADER(ltdlconf.h)
|
||||
|
||||
@ -578,6 +578,10 @@ AC_ARG_ENABLE(cpu-level,
|
||||
echo "ERROR: with >1 processor, use --enable-cpu-level=6"
|
||||
exit 1
|
||||
fi
|
||||
if test "$use_x86_64" = 1 -a "$enableval" -lt 6; then
|
||||
echo "ERROR: --enable-cpu-level=6 required for x86-64 emulation"
|
||||
exit 1
|
||||
fi
|
||||
],
|
||||
[
|
||||
AC_MSG_RESULT(6)
|
||||
@ -1407,28 +1411,6 @@ if test "$support_vmx" -lt 0 -a "$bx_cpu_level" -lt 6; then
|
||||
AC_MSG_ERROR([for VMX support the CPU level must be set to 6])
|
||||
fi
|
||||
|
||||
AC_MSG_CHECKING(for MMX support)
|
||||
AC_ARG_ENABLE(mmx,
|
||||
[ --enable-mmx MMX support],
|
||||
[if test "$enableval" = yes; then
|
||||
AC_MSG_RESULT(yes)
|
||||
AC_DEFINE(BX_SUPPORT_MMX, 1)
|
||||
elif test "$enableval" = no; then
|
||||
AC_MSG_RESULT(no)
|
||||
AC_DEFINE(BX_SUPPORT_MMX, 0)
|
||||
fi
|
||||
],
|
||||
[
|
||||
if test "$bx_cpu_level" -ge 5; then
|
||||
AC_MSG_RESULT(yes)
|
||||
AC_DEFINE(BX_SUPPORT_MMX, 1)
|
||||
else
|
||||
AC_MSG_RESULT(no)
|
||||
AC_DEFINE(BX_SUPPORT_MMX, 0)
|
||||
fi
|
||||
]
|
||||
)
|
||||
|
||||
AC_MSG_CHECKING(for 3DNow! support)
|
||||
AC_ARG_ENABLE(3dnow,
|
||||
[ --enable-3dnow 3DNow! support (incomplete)],
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: cpu.h,v 1.643 2010-03-01 17:35:49 sshwarts Exp $
|
||||
// $Id: cpu.h,v 1.644 2010-03-01 18:53:53 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001-2009 The Bochs Project
|
||||
@ -889,7 +889,7 @@ public: // for now...
|
||||
MSR *msrs[BX_MSR_MAX_INDEX];
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_FPU || BX_SUPPORT_MMX
|
||||
#if BX_SUPPORT_FPU
|
||||
i387_t the_i387;
|
||||
#endif
|
||||
|
||||
@ -3329,9 +3329,11 @@ public: // for now...
|
||||
BX_SMF Bit16u unpack_FPU_TW(Bit16u tag_byte);
|
||||
#endif
|
||||
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_SMF void prepareMMX(void);
|
||||
BX_SMF void prepareFPU2MMX(void); /* cause transition from FPU to MMX technology state */
|
||||
BX_SMF void print_state_MMX(void);
|
||||
#endif
|
||||
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BX_SMF void prepareSSE(void);
|
||||
@ -3415,7 +3417,7 @@ public: // for now...
|
||||
#endif
|
||||
};
|
||||
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPP_INLINE void BX_CPU_C::prepareMMX(void)
|
||||
{
|
||||
if(BX_CPU_THIS_PTR cr0.get_EM())
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: cpuid.cc,v 1.96 2010-03-01 17:35:49 sshwarts Exp $
|
||||
// $Id: cpuid.cc,v 1.97 2010-03-01 18:53:53 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2007-2009 Stanislav Shwartsman
|
||||
@ -66,11 +66,12 @@ Bit32u BX_CPU_C::get_cpu_version_information(void)
|
||||
|
||||
#elif BX_CPU_LEVEL == 5
|
||||
family = 5;
|
||||
#if BX_SUPPORT_MMX
|
||||
model = 4; // Pentium MMX
|
||||
#else
|
||||
model = 1; // Pentium 60/66
|
||||
#endif
|
||||
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_MMX))
|
||||
model = 4; // Pentium MMX
|
||||
else
|
||||
model = 1; // Pentium 60/66
|
||||
|
||||
stepping = 3;
|
||||
|
||||
/* ****** */
|
||||
@ -265,8 +266,10 @@ Bit32u BX_CPU_C::get_std_cpuid_features(void)
|
||||
if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_CLFLUSH)
|
||||
features |= (1<<19);
|
||||
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_MMX)
|
||||
features |= (1<<23);
|
||||
#endif
|
||||
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_P6) {
|
||||
@ -763,6 +766,7 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
|
||||
{
|
||||
Bit32u features_bitmask = 0;
|
||||
|
||||
bx_bool mmx_enabled = SIM->get_param_bool(BXPN_CPUID_MMX)->get();
|
||||
bx_bool sep_enabled = SIM->get_param_bool(BXPN_CPUID_SEP)->get();
|
||||
bx_bool aes_enabled = SIM->get_param_bool(BXPN_CPUID_AES)->get();
|
||||
bx_bool movbe_enabled = SIM->get_param_bool(BXPN_CPUID_MOVBE)->get();
|
||||
@ -771,6 +775,13 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
|
||||
unsigned sse_enabled = SIM->get_param_enum(BXPN_CPUID_SSE)->get();
|
||||
|
||||
// sanity checks
|
||||
#if BX_SUPPORT_3DNOW
|
||||
if (! mmx_enabled) {
|
||||
BX_PANIC(("PANIC: 3DNOW emulation requires MMX support !"));
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (aes_enabled) {
|
||||
// AES required 3-byte opcode (SSS3E support or more)
|
||||
if (sse_enabled < BX_CPUID_SUPPORT_SSSE3) {
|
||||
@ -795,7 +806,7 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
|
||||
}
|
||||
|
||||
if (sse_enabled) {
|
||||
if (BX_SUPPORT_MMX == 0 || BX_CPU_LEVEL < 6) {
|
||||
if (mmx_enabled == 0 || BX_CPU_LEVEL < 6) {
|
||||
BX_PANIC(("PANIC: SSE support requires P6 emulation with MMX enabled !"));
|
||||
return;
|
||||
}
|
||||
@ -836,12 +847,9 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
|
||||
#endif
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
features_bitmask |= BX_CPU_PENTIUM;
|
||||
#endif
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
features_bitmask |= BX_CPU_P6;
|
||||
#endif
|
||||
#if BX_SUPPORT_MMX
|
||||
features_bitmask |= BX_CPU_MMX;
|
||||
|
||||
if (mmx_enabled)
|
||||
features_bitmask |= BX_CPU_MMX;
|
||||
#endif
|
||||
#if BX_SUPPORT_3DNOW
|
||||
features_bitmask |= BX_CPU_3DNOW;
|
||||
@ -851,6 +859,8 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
|
||||
#endif
|
||||
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
features_bitmask |= BX_CPU_P6;
|
||||
|
||||
// enabled CLFLUSH only when SSE2 or higher is enabled
|
||||
if (sse_enabled >= BX_CPUID_SUPPORT_SSE2)
|
||||
features_bitmask |= BX_CPU_CLFLUSH;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: i387.h,v 1.39 2009-10-14 20:45:29 sshwarts Exp $
|
||||
// $Id: i387.h,v 1.40 2010-03-01 18:53:53 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2004-2009 Stanislav Shwartsman
|
||||
@ -178,8 +178,6 @@ BX_CPP_INLINE void i387_t::reset()
|
||||
memset(st_space, 0, sizeof(floatx80)*8);
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_MMX
|
||||
|
||||
typedef union bx_packed_mmx_reg_t {
|
||||
Bit8s _sbyte[8];
|
||||
Bit16s _s16[4];
|
||||
@ -260,8 +258,6 @@ typedef union bx_packed_mmx_reg_t {
|
||||
(BX_FPU_REG(index)).exp = 0xffff; \
|
||||
}
|
||||
|
||||
#endif /* BX_SUPPORT_MMX */
|
||||
|
||||
#endif /* BX_SUPPORT_FPU */
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: init.cc,v 1.228 2010-02-26 22:53:43 sshwarts Exp $
|
||||
// $Id: init.cc,v 1.229 2010-03-01 18:53:53 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001-2009 The Bochs Project
|
||||
@ -482,7 +482,7 @@ void BX_CPU_C::register_state(void)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_FPU || BX_SUPPORT_MMX
|
||||
#if BX_SUPPORT_FPU
|
||||
bx_list_c *fpu = new bx_list_c(cpu, "FPU", 17);
|
||||
BXRS_HEX_PARAM_FIELD(fpu, cwd, the_i387.cwd);
|
||||
BXRS_HEX_PARAM_FIELD(fpu, swd, the_i387.swd);
|
||||
|
||||
192
bochs/cpu/mmx.cc
192
bochs/cpu/mmx.cc
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: mmx.cc,v 1.93 2010-02-26 11:44:50 sshwarts Exp $
|
||||
// $Id: mmx.cc,v 1.94 2010-03-01 18:53:53 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2002-2009 Stanislav Shwartsman
|
||||
@ -26,7 +26,7 @@
|
||||
#include "cpu.h"
|
||||
#define LOG_THIS BX_CPU_THIS_PTR
|
||||
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
|
||||
void BX_CPU_C::print_state_MMX(void)
|
||||
{
|
||||
@ -47,7 +47,7 @@ void BX_CPU_C::prepareFPU2MMX(void)
|
||||
/* 0F 38 00 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -80,7 +80,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 01 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -109,7 +109,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 02 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -136,7 +136,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 03 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -166,7 +166,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHADDSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 04 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDUBSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -199,7 +199,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDUBSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 05 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -229,7 +229,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 05 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -258,7 +258,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 06 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -285,7 +285,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PHSUBD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 08 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -314,7 +314,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 09 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -343,7 +343,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGNW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 0A */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGND_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -374,7 +374,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSIGND_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 0B */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -409,7 +409,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 1C */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
@ -442,7 +442,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 1D */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
@ -471,7 +471,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 38 1E */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
@ -498,7 +498,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PABSD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 3A 0F */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_PqQqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -534,7 +534,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_PqQqIb(bxInstruction_c *i)
|
||||
/* 0F 60 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLBW_PqQd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -568,7 +568,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLBW_PqQd(bxInstruction_c *i)
|
||||
/* 0F 61 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLWD_PqQd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -598,7 +598,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLWD_PqQd(bxInstruction_c *i)
|
||||
/* 0F 62 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLDQ_PqQd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -625,7 +625,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKLDQ_PqQd(bxInstruction_c *i)
|
||||
/* 0F 63 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKSSWB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -659,7 +659,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKSSWB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 64 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -693,7 +693,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 65 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -723,7 +723,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 66 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -751,7 +751,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPGTD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 67 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKUSWB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -785,7 +785,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKUSWB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 68 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHBW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -819,7 +819,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHBW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 69 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHWD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -849,7 +849,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHWD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 6A */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHDQ_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -877,7 +877,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUNPCKHDQ_PqQq(bxInstruction_c *i)
|
||||
/* 0F 6B */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKSSDW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -907,7 +907,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PACKSSDW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 6E */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_PqEdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -923,7 +923,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_PqEdR(bxInstruction_c *i)
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_PqEdM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
@ -958,7 +958,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_PqEqR(bxInstruction_c *i)
|
||||
/* 0F 6F */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_PqQqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -968,7 +968,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_PqQqR(bxInstruction_c *i)
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_PqQqM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op;
|
||||
@ -986,7 +986,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_PqQqM(bxInstruction_c *i)
|
||||
/* 0F 70 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFW_PqQqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op, result;
|
||||
@ -1017,7 +1017,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSHUFW_PqQqIb(bxInstruction_c *i)
|
||||
/* 0F 74 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1051,7 +1051,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQB_PqQq(bxInstruction_c *i)
|
||||
/* 0F 75 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1081,7 +1081,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQW_PqQq(bxInstruction_c *i)
|
||||
/* 0F 76 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1109,7 +1109,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPEQD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 77 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::EMMS(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX || BX_SUPPORT_3DNOW
|
||||
#if BX_SUPPORT_3DNOW
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
FPU_TAG_WORD = 0xffff;
|
||||
FPU_TOS = 0; /* reset FPU Top-Of-Stack */
|
||||
@ -1119,7 +1119,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::EMMS(bxInstruction_c *i)
|
||||
/* 0F 7E */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdPdR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX();
|
||||
|
||||
@ -1130,7 +1130,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdPdR(bxInstruction_c *i)
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdPdM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op = BX_READ_MMX_REG(i->nnn());
|
||||
@ -1161,7 +1161,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_EqPqR(bxInstruction_c *i)
|
||||
/* 0F 7F */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_QqPqR(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX();
|
||||
|
||||
@ -1171,7 +1171,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_QqPqR(bxInstruction_c *i)
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_QqPqM(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op = BX_READ_MMX_REG(i->nnn());
|
||||
@ -1188,7 +1188,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_QqPqM(bxInstruction_c *i)
|
||||
/* 0F C4 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRW_PqEwIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn());
|
||||
@ -1216,7 +1216,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRW_PqEwIb(bxInstruction_c *i)
|
||||
/* 0F C5 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_GdPqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -1230,7 +1230,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_GdPqIb(bxInstruction_c *i)
|
||||
/* 0F D1 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1266,7 +1266,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLW_PqQq(bxInstruction_c *i)
|
||||
/* 0F D2 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1300,7 +1300,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLD_PqQq(bxInstruction_c *i)
|
||||
/* 0F D3 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLQ_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1332,7 +1332,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLQ_PqQq(bxInstruction_c *i)
|
||||
/* 0F D4 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDQ_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1359,7 +1359,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDQ_PqQq(bxInstruction_c *i)
|
||||
/* 0F D5 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULLW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1394,7 +1394,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULLW_PqQq(bxInstruction_c *i)
|
||||
/* 0F D7 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVMSKB_GdPRq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -1418,7 +1418,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVMSKB_GdPRq(bxInstruction_c *i)
|
||||
/* 0F D8 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBUSB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1454,7 +1454,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBUSB_PqQq(bxInstruction_c *i)
|
||||
/* 0F D9 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBUSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1486,7 +1486,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBUSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F DA */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINUB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1520,7 +1520,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINUB_PqQq(bxInstruction_c *i)
|
||||
/* 0F DB */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAND_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1547,7 +1547,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAND_PqQq(bxInstruction_c *i)
|
||||
/* 0F DC */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDUSB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1581,7 +1581,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDUSB_PqQq(bxInstruction_c *i)
|
||||
/* 0F DD */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDUSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1611,7 +1611,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDUSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F DE */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXUB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1645,7 +1645,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXUB_PqQq(bxInstruction_c *i)
|
||||
/* 0F DF */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PANDN_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1672,7 +1672,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PANDN_PqQq(bxInstruction_c *i)
|
||||
/* 0F E0 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAVGB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1706,7 +1706,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAVGB_PqQq(bxInstruction_c *i)
|
||||
/* 0F E1 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1753,7 +1753,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAW_PqQq(bxInstruction_c *i)
|
||||
/* 0F E2 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1797,7 +1797,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAD_PqQq(bxInstruction_c *i)
|
||||
/* 0F E3 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAVGW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -1827,7 +1827,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PAVGW_PqQq(bxInstruction_c *i)
|
||||
/* 0F E4 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHUW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1862,7 +1862,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHUW_PqQq(bxInstruction_c *i)
|
||||
/* 0F E5 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1897,7 +1897,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHW_PqQq(bxInstruction_c *i)
|
||||
/* 0F E7 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTQ_MqPq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister reg = BX_READ_MMX_REG(i->nnn());
|
||||
@ -1912,7 +1912,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTQ_MqPq(bxInstruction_c *i)
|
||||
/* 0F E8 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBSB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1946,7 +1946,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBSB_PqQq(bxInstruction_c *i)
|
||||
/* 0F E9 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -1976,7 +1976,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F EA */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2006,7 +2006,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMINSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F EB */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::POR_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2033,7 +2033,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::POR_PqQq(bxInstruction_c *i)
|
||||
/* 0F EC */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDSB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -2067,7 +2067,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDSB_PqQq(bxInstruction_c *i)
|
||||
/* 0F ED */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -2097,7 +2097,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F EE */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXSW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2127,7 +2127,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMAXSW_PqQq(bxInstruction_c *i)
|
||||
/* 0F EF */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PXOR_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2154,7 +2154,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PXOR_PqQq(bxInstruction_c *i)
|
||||
/* 0F F1 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2190,7 +2190,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLW_PqQq(bxInstruction_c *i)
|
||||
/* 0F F2 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2224,7 +2224,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLD_PqQq(bxInstruction_c *i)
|
||||
/* 0F F3 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLQ_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2256,7 +2256,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLQ_PqQq(bxInstruction_c *i)
|
||||
/* 0F F4 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULUDQ_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -2283,7 +2283,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULUDQ_PqQq(bxInstruction_c *i)
|
||||
/* 0F F5 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDWD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
|
||||
@ -2322,7 +2322,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMADDWD_PqQq(bxInstruction_c *i)
|
||||
/* 0F F6 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSADBW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2359,7 +2359,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSADBW_PqQq(bxInstruction_c *i)
|
||||
/* 0F F7 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MASKMOVQ_PqPRq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_3DNOW || BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -2401,7 +2401,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MASKMOVQ_PqPRq(bxInstruction_c *i)
|
||||
/* 0F F8 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2435,7 +2435,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBB_PqQq(bxInstruction_c *i)
|
||||
/* 0F F9 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2465,7 +2465,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBW_PqQq(bxInstruction_c *i)
|
||||
/* 0F FA */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2493,7 +2493,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBD_PqQq(bxInstruction_c *i)
|
||||
/* 0F FB */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBQ_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2520,7 +2520,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSUBQ_PqQq(bxInstruction_c *i)
|
||||
/* 0F FC */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDB_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2554,7 +2554,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDB_PqQq(bxInstruction_c *i)
|
||||
/* 0F FD */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDW_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2584,7 +2584,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDW_PqQq(bxInstruction_c *i)
|
||||
/* 0F FE */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDD_PqQq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
|
||||
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2;
|
||||
@ -2612,7 +2612,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PADDD_PqQq(bxInstruction_c *i)
|
||||
/* 0F 71 GrpA 010 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLW_PqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -2636,7 +2636,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLW_PqIb(bxInstruction_c *i)
|
||||
/* 0F 71 GrpA 100 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAW_PqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -2671,7 +2671,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAW_PqIb(bxInstruction_c *i)
|
||||
/* 0F 71 GrpA 110 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLW_PqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -2695,7 +2695,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLW_PqIb(bxInstruction_c *i)
|
||||
/* 0F 72 GrpA 010 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLD_PqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -2717,7 +2717,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLD_PqIb(bxInstruction_c *i)
|
||||
/* 0F 72 GrpA 100 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAD_PqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -2749,7 +2749,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRAD_PqIb(bxInstruction_c *i)
|
||||
/* 0F 72 GrpA 110 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLD_PqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -2771,7 +2771,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLD_PqIb(bxInstruction_c *i)
|
||||
/* 0F 73 GrpA 010 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLQ_PqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
@ -2793,7 +2793,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSRLQ_PqIb(bxInstruction_c *i)
|
||||
/* 0F 73 GrpA 110 */
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PSLLQ_PqIb(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_SUPPORT_MMX
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_CPU_THIS_PTR prepareMMX();
|
||||
BX_CPU_THIS_PTR prepareFPU2MMX(); /* FPU2MMX transition */
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: sse_move.cc,v 1.109 2010-02-26 11:44:50 sshwarts Exp $
|
||||
// $Id: sse_move.cc,v 1.110 2010-03-01 18:53:53 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003-2009 Stanislav Shwartsman
|
||||
@ -159,13 +159,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
|
||||
|
||||
BX_DEBUG(("FXSAVE: save FPU/MMX/SSE state"));
|
||||
|
||||
#if BX_SUPPORT_MMX
|
||||
if(BX_CPU_THIS_PTR cr0.get_TS())
|
||||
exception(BX_NM_EXCEPTION, 0, 0);
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_MMX))
|
||||
{
|
||||
if(BX_CPU_THIS_PTR cr0.get_TS())
|
||||
exception(BX_NM_EXCEPTION, 0, 0);
|
||||
|
||||
if(BX_CPU_THIS_PTR cr0.get_EM())
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
#endif
|
||||
if(BX_CPU_THIS_PTR cr0.get_EM())
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
}
|
||||
|
||||
xmm.xmm16u(0) = BX_CPU_THIS_PTR the_i387.get_control_word();
|
||||
xmm.xmm16u(1) = BX_CPU_THIS_PTR the_i387.get_status_word();
|
||||
@ -278,13 +279,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
|
||||
|
||||
BX_DEBUG(("FXRSTOR: restore FPU/MMX/SSE state"));
|
||||
|
||||
#if BX_SUPPORT_MMX
|
||||
if(BX_CPU_THIS_PTR cr0.get_TS())
|
||||
exception(BX_NM_EXCEPTION, 0, 0);
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_MMX)) {
|
||||
if(BX_CPU_THIS_PTR cr0.get_TS())
|
||||
exception(BX_NM_EXCEPTION, 0, 0);
|
||||
|
||||
if(BX_CPU_THIS_PTR cr0.get_EM())
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
#endif
|
||||
if(BX_CPU_THIS_PTR cr0.get_EM())
|
||||
exception(BX_UD_EXCEPTION, 0, 0);
|
||||
}
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
<!--
|
||||
================================================================
|
||||
doc/docbook/user/user.dbk
|
||||
$Id: user.dbk,v 1.275 2010-02-26 22:53:43 sshwarts Exp $
|
||||
$Id: user.dbk,v 1.276 2010-03-01 18:53:53 sshwarts Exp $
|
||||
|
||||
This is the top level file for the Bochs Users Manual.
|
||||
================================================================
|
||||
@ -2040,7 +2040,7 @@ turn it off.
|
||||
<tbody>
|
||||
<row id="configure-enable-cpu-level">
|
||||
<entry>--enable-cpu-level={<option>3,4,5,6</option>}</entry>
|
||||
<entry>5</entry>
|
||||
<entry>6</entry>
|
||||
<entry>
|
||||
Select which CPU level to emulate. Choices are 3,4,5,6 which mean to
|
||||
target 386, 486, Pentium, or Pentium Pro and later emulation.
|
||||
@ -2079,18 +2079,6 @@ turn it off.
|
||||
<entry>no</entry>
|
||||
<entry>support for 1G page extensions in x86-64 long mode</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>--enable-xapic</entry>
|
||||
<entry>no</entry>
|
||||
<entry>support for XAPIC extensions</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>--enable-mmx</entry>
|
||||
<entry>no (yes for <link linkend="configure-enable-cpu-level">CPU</link> >= 5)</entry>
|
||||
<entry>
|
||||
Add support for MMX instructions, written by Stanislav Shwartsman.
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>--enable-vmx</entry>
|
||||
<entry>no</entry>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: main.cc,v 1.415 2010-02-28 14:52:16 sshwarts Exp $
|
||||
// $Id: main.cc,v 1.416 2010-03-01 18:53:53 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001-2009 The Bochs Project
|
||||
@ -992,10 +992,15 @@ void bx_init_hardware()
|
||||
|
||||
io->set_log_prefix(SIM->get_param_string(BXPN_LOG_PREFIX)->getptr());
|
||||
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
bx_bool mmx_enabled = SIM->get_param_bool(BXPN_CPUID_MMX)->get();
|
||||
#endif
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
bx_bool aes_enabled = SIM->get_param_bool(BXPN_CPUID_AES)->get();
|
||||
bx_bool movbe_enabled = SIM->get_param_bool(BXPN_CPUID_MOVBE)->get();
|
||||
bx_bool sep_enabled = SIM->get_param_bool(BXPN_CPUID_SEP)->get();
|
||||
bx_bool xsave_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVE)->get();
|
||||
#endif
|
||||
|
||||
// Output to the log file the cpu and device settings
|
||||
// This will by handy for bug reports
|
||||
@ -1019,19 +1024,23 @@ void bx_init_hardware()
|
||||
#endif
|
||||
BX_INFO((" APIC support: %s",BX_SUPPORT_APIC?"yes":"no"));
|
||||
BX_INFO((" FPU support: %s",BX_SUPPORT_FPU?"yes":"no"));
|
||||
BX_INFO((" MMX support: %s",BX_SUPPORT_MMX?"yes":"no"));
|
||||
BX_INFO((" SSE support: %s", SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected()));
|
||||
#if BX_CPU_LEVEL >= 5
|
||||
BX_INFO((" MMX support: %s",mmx_enabled?"yes":"no"));
|
||||
BX_INFO((" 3dnow! support: %s",BX_SUPPORT_3DNOW?"yes":"no"));
|
||||
#endif
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BX_INFO((" SEP support: %s",sep_enabled?"yes":"no"));
|
||||
BX_INFO((" SSE support: %s", SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected()));
|
||||
BX_INFO((" XSAVE support: %s",xsave_enabled?"yes":"no"));
|
||||
BX_INFO((" AES support: %s",aes_enabled?"yes":"no"));
|
||||
BX_INFO((" MOVBE support: %s",movbe_enabled?"yes":"no"));
|
||||
#if BX_SUPPORT_X86_64
|
||||
BX_INFO((" 1G paging support: %s",BX_SUPPORT_1G_PAGES?"yes":"no"));
|
||||
#endif
|
||||
BX_INFO((" x86-64 support: %s",BX_SUPPORT_X86_64?"yes":"no"));
|
||||
BX_INFO((" SEP support: %s",sep_enabled?"yes":"no"));
|
||||
BX_INFO((" MWAIT support: %s",BX_SUPPORT_MONITOR_MWAIT?"yes":"no"));
|
||||
BX_INFO((" XSAVE support: %s",xsave_enabled?"yes":"no"));
|
||||
BX_INFO((" AES support: %s",aes_enabled?"yes":"no"));
|
||||
BX_INFO((" MOVBE support: %s",movbe_enabled?"yes":"no"));
|
||||
BX_INFO((" VMX support: %s",BX_SUPPORT_VMX?"yes":"no"));
|
||||
#endif
|
||||
BX_INFO(("Optimization configuration"));
|
||||
BX_INFO((" RepeatSpeedups support: %s",BX_SupportRepeatSpeedups?"yes":"no"));
|
||||
BX_INFO((" Trace cache support: %s",BX_SUPPORT_TRACE_CACHE?"yes":"no"));
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: param_names.h,v 1.3 2010-02-28 14:52:16 sshwarts Exp $
|
||||
// $Id: param_names.h,v 1.4 2010-03-01 18:53:53 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2009 The Bochs Project
|
||||
@ -43,6 +43,7 @@
|
||||
#define BXPN_VENDOR_STRING "cpuid.vendor_string"
|
||||
#define BXPN_BRAND_STRING "cpuid.brand_string"
|
||||
#define BXPN_CPUID_LIMIT_WINNT "cpuid.cpuid_limit_winnt"
|
||||
#define BXPN_CPUID_MMX "cpuid.mmx"
|
||||
#define BXPN_CPUID_SSE "cpuid.sse"
|
||||
#define BXPN_CPUID_AES "cpuid.aes"
|
||||
#define BXPN_CPUID_MOVBE "cpuid.movbe"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user