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IA32_FEATURE_CONTROL_MSR is implemented

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This commit is contained in:
Stanislav Shwartsman 2010-03-06 16:59:05 +00:00
parent ef4731ef49
commit 5d2c2879a7
5 changed files with 47 additions and 15 deletions
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7
bochs/cpu/cpu.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.645 2010-03-05 08:54:07 sshwarts Exp $
// $Id: cpu.h,v 1.646 2010-03-06 16:59:04 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
@ -357,6 +357,7 @@ enum {
#define BX_MSR_VMX_TRUE_PROCBASED_CTRLS 0x48e
#define BX_MSR_VMX_TRUE_VMEXIT_CTRLS 0x48f
#define BX_MSR_VMX_TRUE_VMENTRY_CTRLS 0x490
#define BX_MSR_IA32_FEATURE_CONTROL 0x03A
#define BX_MSR_IA32_SMM_MONITOR_CTL 0x09B
#endif
@ -589,6 +590,10 @@ typedef struct
Bit64u pat;
#endif
#if BX_SUPPORT_VMX
Bit32u ia32_feature_ctrl;
#endif
/* TODO finish of the others */
} bx_regs_msr_t;
#endif

4
bochs/cpu/init.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.230 2010-03-05 08:54:07 sshwarts Exp $
// $Id: init.cc,v 1.231 2010-03-06 16:59:05 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
@ -1030,6 +1030,8 @@ void BX_CPU_C::reset(unsigned source)
BX_CPU_THIS_PTR vmx_interrupt_window = 0;
BX_CPU_THIS_PTR vmcsptr = BX_CPU_THIS_PTR vmxonptr = BX_INVALID_VMCSPTR;
BX_CPU_THIS_PTR vmcshostptr = 0;
BX_CPU_THIS_PTR msr.ia32_feature_ctrl = 0x4; /* enable VMX, should be done in BIOS instead */
#endif
#if BX_SUPPORT_SMP

17
bochs/cpu/msr.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: msr.cc,v 1.33 2010-03-05 08:54:07 sshwarts Exp $
// $Id: msr.cc,v 1.34 2010-03-06 16:59:05 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2009 Stanislav Shwartsman
@ -140,6 +140,9 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
BX_PANIC(("Dual-monitor treatment of SMI and SMM is not implemented"));
break;
*/
case BX_MSR_IA32_FEATURE_CONTROL:
val64 = BX_CPU_THIS_PTR msr.ia32_feature_ctrl;
break;
case BX_MSR_VMX_BASIC:
val64 = VMX_MSR_VMX_BASIC;
break;
@ -467,6 +470,18 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
#endif
#if BX_SUPPORT_VMX
// Support only two bits: lock bit (bit 0) and VMX enable (bit 2)
case BX_MSR_IA32_FEATURE_CONTROL:
if (BX_CPU_THIS_PTR msr.ia32_feature_ctrl & 0x1) {
BX_ERROR(("WRMSR: IA32_FEATURE_CONTROL_MSR VMX lock bit is set !"));
return 0;
}
if (val_64 & ~((Bit64u)(BX_IA32_FEATURE_CONTROL_BITS))) {
BX_ERROR(("WRMSR: attempt to set reserved bits of IA32_FEATURE_CONTROL_MSR !"));
return 0;
}
BX_CPU_THIS_PTR msr.ia32_feature_ctrl = val32_lo;
case BX_MSR_VMX_BASIC:
case BX_MSR_VMX_PINBASED_CTRLS:
case BX_MSR_VMX_PROCBASED_CTRLS:

25
bochs/cpu/vmx.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vmx.cc,v 1.30 2010-02-06 20:52:27 sshwarts Exp $
// $Id: vmx.cc,v 1.31 2010-03-06 16:59:05 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2009 Stanislav Shwartsman
@ -1817,24 +1817,27 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::VMXON(bxInstruction_c *i)
if (! BX_CPU_THIS_PTR in_vmx) {
if (CPL != 0 || ! BX_CPU_THIS_PTR cr0.get_NE() ||
! BX_CPU_THIS_PTR cr0.get_PE() || BX_GET_ENABLE_A20() == 0 /* ||
(bit 0 (lock bit) of IA32_FEATURE_CONTROL MSR is clear) ||
(bit 2 of IA32_FEATURE_CONTROL MSR is clear)*/)
exception(BX_GP_EXCEPTION, 0, 0);
! (BX_CPU_THIS_PTR cr0.get_PE()) || BX_GET_ENABLE_A20() == 0 ||
! (BX_CPU_THIS_PTR msr.ia32_feature_ctrl & BX_IA32_FEATURE_CONTROL_LOCK_BIT) ||
! (BX_CPU_THIS_PTR msr.ia32_feature_ctrl & BX_IA32_FEATURE_CONTROL_VMX_ENABLE_BIT))
{
BX_ERROR(("#GP: VMXON is not allowed !"));
exception(BX_GP_EXCEPTION, 0, 0);
}
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit64u pAddr = read_virtual_qword(i->seg(), eaddr); // keep 64-bit
if ((pAddr & 0xfff) != 0 || ! IsValidPhyAddr(pAddr)) {
BX_ERROR(("VMXON: invalid or not page aligned physical address !"));
VMfailInvalid();
return;
BX_ERROR(("VMXON: invalid or not page aligned physical address !"));
VMfailInvalid();
return;
}
Bit32u revision = VMXReadRevisionID((bx_phy_address) pAddr);
if (revision != VMX_VMCS_REVISION_ID) {
BX_ERROR(("VMXON: not expected (%d != %d) VMCS revision id !", revision, VMX_VMCS_REVISION_ID));
VMfailInvalid();
return;
BX_ERROR(("VMXON: not expected (%d != %d) VMCS revision id !", revision, VMX_VMCS_REVISION_ID));
VMfailInvalid();
return;
}
BX_CPU_THIS_PTR vmcsptr = BX_INVALID_VMCSPTR;

9
bochs/cpu/vmx.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vmx.h,v 1.8 2010-02-11 14:19:11 sshwarts Exp $
// $Id: vmx.h,v 1.9 2010-03-06 16:59:05 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2009 Stanislav Shwartsman
@ -30,6 +30,13 @@
// VMCS pointer is always 64-bit variable
#define BX_INVALID_VMCSPTR BX_CONST64(0xFFFFFFFFFFFFFFFF)
// bits supported in IA32_FEATURE_CONTROL MSR
#define BX_IA32_FEATURE_CONTROL_LOCK_BIT 0x1
#define BX_IA32_FEATURE_CONTROL_VMX_ENABLE_BIT 0x4
#define BX_IA32_FEATURE_CONTROL_BITS \
(BX_IA32_FEATURE_CONTROL_LOCK_BIT | BX_IA32_FEATURE_CONTROL_VMX_ENABLE_BIT)
// VMX error codes
enum VMX_error_code {
VMXERR_NO_ERROR = 0,