changes variable name to better one
This commit is contained in:
Stanislav Shwartsman
parent
93220f6b6e
commit
d39d485ece
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dbg_main.cc,v 1.234 2010-03-31 14:00:46 sshwarts Exp $
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// $Id: dbg_main.cc,v 1.235 2010-04-03 05:59:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2009 The Bochs Project
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@ -665,9 +665,9 @@ void bx_dbg_exit(int code)
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void bx_dbg_print_sse_state(void)
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{
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#if BX_CPU_LEVEL >= 6
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Bit32u cpuid_features_bitmask = SIM->get_param_num("cpuid_features_bitmask", dbg_cpu_list)->get();
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Bit32u isa_extensions_bitmask = SIM->get_param_num("isa_extensions_bitmask", dbg_cpu_list)->get();
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if ((cpuid_features_bitmask & BX_CPU_SSE) != 0) {
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if ((isa_extensions_bitmask & BX_CPU_SSE) != 0) {
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Bit32u mxcsr = SIM->get_param_num("SSE.mxcsr", dbg_cpu_list)->get();
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dbg_printf("MXCSR: 0x%08x: %s %s RC:%d %s %s %s %s %s %s %s %s %s %s %s %s %s\n", mxcsr,
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(mxcsr & (1<<17)) ? "ULE" : "ule",
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@ -707,9 +707,9 @@ void bx_dbg_print_sse_state(void)
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void bx_dbg_print_mmx_state(void)
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{
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#if BX_CPU_LEVEL >= 5
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Bit32u cpuid_features_bitmask = SIM->get_param_num("cpuid_features_bitmask", dbg_cpu_list)->get();
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Bit32u isa_extensions_bitmask = SIM->get_param_num("isa_extensions_bitmask", dbg_cpu_list)->get();
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if ((cpuid_features_bitmask & BX_CPU_MMX) != 0) {
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if ((isa_extensions_bitmask & BX_CPU_MMX) != 0) {
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char param_name[20];
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for(unsigned i=0;i<8;i++) {
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sprintf(param_name, "FPU.st%d.fraction", i);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: apic.cc,v 1.138 2010-03-27 09:56:30 sshwarts Exp $
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// $Id: apic.cc,v 1.139 2010-04-03 05:59:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2002-2009 Zwane Mwaikambo, Stanislav Shwartsman
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@ -187,6 +187,12 @@ bx_local_apic_c::bx_local_apic_c(BX_CPU_C *mycpu, unsigned id)
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BX_CPU(0)->lapic.periodic_smf, 0, 0, 0, "lapic");
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timer_active = 0;
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#if BX_CPU_LEVEL >= 6
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xapic = SIM->get_param_bool(BXPN_CPUID_XAPIC)->get();
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#else
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xapic = 0;
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#endif
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reset(BX_RESET_HARDWARE);
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.661 2010-04-02 19:03:47 sshwarts Exp $
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// $Id: cpu.h,v 1.662 2010-04-03 05:59:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2010 The Bochs Project
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@ -629,8 +629,6 @@ typedef struct
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#define BX_CPU_AVX 0x00800000 /* AVX instruction */
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#define BX_CPU_AVX_FMA 0x01000000 /* AVX FMA instruction */
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#define BX_CPU_X86_64 0x02000000 /* x86-64 instruction */
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#define BX_CPU_XAPIC 0x04000000 /* XAPIC extensions */
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#define BX_CPU_X2APIC 0x08000000 /* X2APIC extensions */
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struct cpuid_function_t {
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Bit32u eax;
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@ -800,10 +798,10 @@ public: // for now...
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cpuid_function_t cpuid_std_function[MAX_STD_CPUID_FUNCTION];
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cpuid_function_t cpuid_ext_function[MAX_EXT_CPUID_FUNCTION];
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Bit32u cpuid_features_bitmask;
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Bit32u isa_extensions_bitmask;
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#define BX_CPU_SUPPORT_FEATURE(feature) \
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(BX_CPU_THIS_PTR cpuid_features_bitmask & (feature))
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#define BX_CPU_SUPPORT_ISA_EXTENSION(feature) \
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(BX_CPU_THIS_PTR isa_extensions_bitmask & (feature))
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// General register set
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// rax: accumulator
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@ -3251,7 +3249,7 @@ public: // for now...
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BX_SMF Bit32u get_std_cpuid_features(void);
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BX_SMF void set_cpuid_defaults(void);
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BX_SMF void init_cpu_features_bitmask(void);
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BX_SMF void init_isa_features_bitmask(void);
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BX_SMF void init_FetchDecodeTables(void);
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BX_SMF BX_CPP_INLINE unsigned which_cpu(void) { return BX_CPU_THIS_PTR bx_cpuid; }
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpuid.cc,v 1.110 2010-03-31 14:00:46 sshwarts Exp $
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// $Id: cpuid.cc,v 1.111 2010-04-03 05:59:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2007-2010 Stanislav Shwartsman
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@ -76,7 +76,7 @@ Bit32u BX_CPU_C::get_cpu_version_information(void)
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#elif BX_CPU_LEVEL == 5
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family = 5;
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if (BX_CPU_SUPPORT_FEATURE(BX_CPU_MMX))
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if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_MMX))
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model = 4; // Pentium MMX
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else
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model = 1; // Pentium 60/66
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@ -164,47 +164,47 @@ Bit32u BX_CPU_C::get_extended_cpuid_features(void)
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Bit32u features = 0;
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// support SSE3
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE3)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE3)
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features |= (1<<0);
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// support for PCLMULQDQ
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_AES_PCLMULQDQ)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_AES_PCLMULQDQ)
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features |= (1<<1);
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_MONITOR_MWAIT)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_MONITOR_MWAIT)
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features |= (1<<3);
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_VMX)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_VMX)
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features |= (1<<5);
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSSE3)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSSE3)
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features |= (1<<9);
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#if BX_SUPPORT_X86_64
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// support CMPXCHG16B
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_X86_64)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_X86_64)
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features |= (1<<13);
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#endif
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE4_1)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE4_1)
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features |= (1<<19);
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE4_2)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE4_2)
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features |= (1<<20);
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_MOVBE)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_MOVBE)
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features |= (1<<22);
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// enable POPCNT if SSE4_2 is enabled
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE4_2)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE4_2)
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features |= (1<<23);
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// support for AES
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_AES_PCLMULQDQ)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_AES_PCLMULQDQ)
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features |= (1<<25);
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// support XSAVE extensions
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_XSAVE)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_XSAVE)
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features |= (1<<26) | (1<<27);
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return features;
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@ -248,11 +248,11 @@ Bit32u BX_CPU_C::get_std_cpuid_features(void)
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Bit32u features = 0;
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_X87)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_X87)
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features |= (1<<0);
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_PENTIUM) {
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_PENTIUM) {
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// Pentium only features
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features |= (1<<1); // support VME
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features |= (1<<3); // support PSE
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@ -272,19 +272,19 @@ Bit32u BX_CPU_C::get_std_cpuid_features(void)
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features |= (1<<9); // APIC on chip
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#endif
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SYSENTER_SYSEXIT)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SYSENTER_SYSEXIT)
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features |= (1<<11);
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_CLFLUSH)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_CLFLUSH)
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features |= (1<<19);
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#if BX_CPU_LEVEL >= 5
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_MMX)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_MMX)
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features |= (1<<23);
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#endif
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#if BX_CPU_LEVEL >= 6
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_P6) {
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_P6) {
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features |= (1<<6); // support PAE
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features |= (1<<12); // support MTRRs
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features |= (1<<13); // support Global pages
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@ -293,13 +293,13 @@ Bit32u BX_CPU_C::get_std_cpuid_features(void)
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features |= (1<<17); // support PSE-36
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}
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_FXSAVE_FXRSTOR)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_FXSAVE_FXRSTOR)
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features |= (1<<24); // support FSAVE/FXRSTOR instructions
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE)
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features |= (1<<25);
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if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE2)
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if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE2)
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features |= (1<<26);
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#endif
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@ -406,7 +406,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
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if (! cpuid_limit_winnt) {
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if (BX_SUPPORT_MONITOR_MWAIT)
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cpuid->eax = 0x5;
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if (BX_CPU_SUPPORT_FEATURE(BX_CPU_XSAVE))
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if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE))
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cpuid->eax = 0xD;
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}
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#endif
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@ -437,7 +437,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
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// [31:24] Local Apic ID
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cpuid->ebx = 0;
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if (BX_CPU_SUPPORT_FEATURE(BX_CPU_CLFLUSH)) {
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if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_CLFLUSH)) {
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cpuid->ebx |= (CACHE_LINE_SIZE / 8) << 8;
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}
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unsigned n_logical_processors = SIM->get_param_num(BXPN_CPU_NCORES)->get()*SIM->get_param_num(BXPN_CPU_NTHREADS)->get();
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@ -583,7 +583,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
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// ------------------------------------------------------
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// CPUID function 0x0000000D
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if (BX_CPU_SUPPORT_FEATURE(BX_CPU_XSAVE))
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if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE))
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{
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cpuid = &(BX_CPU_THIS_PTR cpuid_std_function[0xD]);
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@ -600,7 +600,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
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}
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// do not report Pentium 4 extended functions if not needed
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if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE2))
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if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE2))
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return;
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// ------------------------------------------------------
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@ -792,7 +792,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
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#endif // BX_CPU_LEVEL >= 6
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}
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void BX_CPU_C::init_cpu_features_bitmask(void)
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void BX_CPU_C::init_isa_features_bitmask(void)
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{
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Bit32u features_bitmask = 0;
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@ -946,9 +946,6 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
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if (movbe_enabled)
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features_bitmask |= BX_CPU_MOVBE;
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if (xapic_enabled)
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features_bitmask |= BX_CPU_XAPIC;
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#endif
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#if BX_SUPPORT_VMX
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@ -959,5 +956,5 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
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features_bitmask |= BX_CPU_X86_64;
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#endif
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BX_CPU_THIS_PTR cpuid_features_bitmask = features_bitmask;
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BX_CPU_THIS_PTR isa_extensions_bitmask = features_bitmask;
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: crregs.cc,v 1.4 2010-03-31 14:00:46 sshwarts Exp $
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// $Id: crregs.cc,v 1.5 2010-04-03 05:59:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2010 Stanislav Shwartsman
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@ -889,7 +889,7 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR0(bx_address val)
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}
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#if BX_CPU_LEVEL >= 4
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bx_address get_cr4_allow_mask(Bit32u cpuid_features_bitmask)
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bx_address get_cr4_allow_mask(Bit32u isa_extensions_bitmask)
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{
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bx_address allowMask = 0;
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@ -941,11 +941,11 @@ bx_address get_cr4_allow_mask(Bit32u cpuid_features_bitmask)
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allowMask |= (1<<8); /* PCE */
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/* OSFXSR */
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if (cpuid_features_bitmask & BX_CPU_FXSAVE_FXRSTOR)
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if (isa_extensions_bitmask & BX_CPU_FXSAVE_FXRSTOR)
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allowMask |= (1<<9); /* OSFXSR */
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/* OSXMMECPT */
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if (cpuid_features_bitmask & BX_CPU_SSE)
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if (isa_extensions_bitmask & BX_CPU_SSE)
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allowMask |= (1<<10);
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#endif
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@ -959,7 +959,7 @@ bx_address get_cr4_allow_mask(Bit32u cpuid_features_bitmask)
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#if BX_CPU_LEVEL >= 6
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/* OSXSAVE */
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if (cpuid_features_bitmask & BX_CPU_XSAVE)
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if (isa_extensions_bitmask & BX_CPU_XSAVE)
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allowMask |= (1<<18);
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#endif
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@ -969,7 +969,7 @@ bx_address get_cr4_allow_mask(Bit32u cpuid_features_bitmask)
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bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::check_CR4(bx_address cr4_val)
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{
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bx_cr4_t temp_cr4;
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bx_address cr4_allow_mask = get_cr4_allow_mask(BX_CPU_THIS_PTR cpuid_features_bitmask);
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bx_address cr4_allow_mask = get_cr4_allow_mask(BX_CPU_THIS_PTR isa_extensions_bitmask);
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temp_cr4.val32 = (Bit32u) cr4_val;
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#if BX_SUPPORT_X86_64
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: fetchdecode.cc,v 1.262 2010-03-31 14:03:06 sshwarts Exp $
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// $Id: fetchdecode.cc,v 1.263 2010-04-03 05:59:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2009 The Bochs Project
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@ -2907,7 +2907,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BxError(bxInstruction_c *i)
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}
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else {
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BX_INFO(("%s: instruction not supported - signalling #UD (features bitmask: 0x%08x)",
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get_bx_opcode_name(ia_opcode), BX_CPU_THIS_PTR cpuid_features_bitmask));
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get_bx_opcode_name(ia_opcode), BX_CPU_THIS_PTR isa_extensions_bitmask));
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}
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exception(BX_UD_EXCEPTION, 0);
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@ -2934,7 +2934,7 @@ void BX_CPU_C::init_FetchDecodeTables(void)
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};
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#undef bx_define_opcode
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Bit32u features = BX_CPU_THIS_PTR cpuid_features_bitmask;
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Bit32u features = BX_CPU_THIS_PTR isa_extensions_bitmask;
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if (! features)
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BX_PANIC(("init_FetchDecodeTables: CPU features bitmask is empty !"));
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: init.cc,v 1.235 2010-03-26 11:09:12 sshwarts Exp $
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// $Id: init.cc,v 1.236 2010-04-03 05:59:07 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2009 The Bochs Project
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@ -152,8 +152,8 @@ void BX_CPU_C::initialize(void)
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{
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BX_CPU_THIS_PTR set_INTR(0);
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init_cpu_features_bitmask();
|
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init_FetchDecodeTables(); // must be called after init_cpu_features_bitmask()
|
||||
init_isa_features_bitmask();
|
||||
init_FetchDecodeTables(); // must be called after init_isa_features_bitmask()
|
||||
|
||||
#if BX_CONFIGURE_MSRS
|
||||
for (unsigned n=0; n < BX_MSR_MAX_INDEX; n++) {
|
||||
@ -312,7 +312,7 @@ void BX_CPU_C::register_state(void)
|
||||
BXRS_PARAM_SPECIAL32(cpu, cpu_version, param_save_handler, param_restore_handler);
|
||||
BXRS_PARAM_SPECIAL32(cpu, cpuid_std, param_save_handler, param_restore_handler);
|
||||
BXRS_PARAM_SPECIAL32(cpu, cpuid_ext, param_save_handler, param_restore_handler);
|
||||
BXRS_HEX_PARAM_SIMPLE(cpu, cpuid_features_bitmask);
|
||||
BXRS_HEX_PARAM_SIMPLE(cpu, isa_extensions_bitmask);
|
||||
BXRS_DEC_PARAM_SIMPLE(cpu, cpu_mode);
|
||||
BXRS_HEX_PARAM_SIMPLE(cpu, activity_state);
|
||||
BXRS_HEX_PARAM_SIMPLE(cpu, inhibit_mask);
|
||||
@ -363,7 +363,7 @@ void BX_CPU_C::register_state(void)
|
||||
BXRS_HEX_PARAM_FIELD(cpu, CR4, cr4.val32);
|
||||
#endif
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_XSAVE)) {
|
||||
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE)) {
|
||||
BXRS_HEX_PARAM_FIELD(cpu, XCR0, xcr0.val32);
|
||||
}
|
||||
#endif
|
||||
@ -511,7 +511,7 @@ void BX_CPU_C::register_state(void)
|
||||
#endif
|
||||
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE)) {
|
||||
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE)) {
|
||||
bx_list_c *sse = new bx_list_c(cpu, "SSE", 2*BX_XMM_REGISTERS+1);
|
||||
BXRS_HEX_PARAM_FIELD(sse, mxcsr, mxcsr.mxcsr);
|
||||
for (n=0; n<BX_XMM_REGISTERS; n++) {
|
||||
@ -1027,7 +1027,7 @@ void BX_CPU_C::reset(unsigned source)
|
||||
|
||||
BX_CPU_THIS_PTR mxcsr.mxcsr = MXCSR_RESET;
|
||||
BX_CPU_THIS_PTR mxcsr_mask = 0x0000FFBF;
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE2))
|
||||
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE2))
|
||||
BX_CPU_THIS_PTR mxcsr_mask |= MXCSR_DAZ;
|
||||
if (BX_SUPPORT_MISALIGNED_SSE)
|
||||
BX_CPU_THIS_PTR mxcsr_mask |= MXCSR_MISALIGNED_EXCEPTION_MASK;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: msr.cc,v 1.43 2010-03-26 21:26:08 sshwarts Exp $
|
||||
// $Id: msr.cc,v 1.44 2010-04-03 05:59:07 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2008-2009 Stanislav Shwartsman
|
||||
@ -44,7 +44,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
|
||||
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
case BX_MSR_SYSENTER_CS:
|
||||
if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
// failed to find the MSR, could #GP or ignore it silently
|
||||
BX_ERROR(("RDMSR MSR_SYSENTER_CS: SYSENTER/SYSEXIT feature not enabled !"));
|
||||
if (! BX_CPU_THIS_PTR ignore_bad_msrs)
|
||||
@ -54,7 +54,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
|
||||
break;
|
||||
|
||||
case BX_MSR_SYSENTER_ESP:
|
||||
if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
// failed to find the MSR, could #GP or ignore it silently
|
||||
BX_ERROR(("RDMSR MSR_SYSENTER_ESP: SYSENTER/SYSEXIT feature not enabled !"));
|
||||
if (! BX_CPU_THIS_PTR ignore_bad_msrs)
|
||||
@ -64,7 +64,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
|
||||
break;
|
||||
|
||||
case BX_MSR_SYSENTER_EIP:
|
||||
if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
// failed to find the MSR, could #GP or ignore it silently
|
||||
BX_ERROR(("RDMSR MSR_SYSENTER_EIP: SYSENTER/SYSEXIT feature not enabled !"));
|
||||
if (! BX_CPU_THIS_PTR ignore_bad_msrs)
|
||||
@ -328,7 +328,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
|
||||
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
case BX_MSR_SYSENTER_CS:
|
||||
if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
// failed to find the MSR, could #GP or ignore it silently
|
||||
BX_ERROR(("WRMSR MSR_SYSENTER_CS: SYSENTER/SYSEXIT feature not enabled !"));
|
||||
if (! BX_CPU_THIS_PTR ignore_bad_msrs)
|
||||
@ -338,7 +338,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
|
||||
break;
|
||||
|
||||
case BX_MSR_SYSENTER_ESP:
|
||||
if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
// failed to find the MSR, could #GP or ignore it silently
|
||||
BX_ERROR(("WRMSR MSR_SYSENTER_ESP: SYSENTER/SYSEXIT feature not enabled !"));
|
||||
if (! BX_CPU_THIS_PTR ignore_bad_msrs)
|
||||
@ -354,7 +354,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
|
||||
break;
|
||||
|
||||
case BX_MSR_SYSENTER_EIP:
|
||||
if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
|
||||
// failed to find the MSR, could #GP or ignore it silently
|
||||
BX_ERROR(("WRMSR MSR_SYSENTER_EIP: SYSENTER/SYSEXIT feature not enabled !"));
|
||||
if (! BX_CPU_THIS_PTR ignore_bad_msrs)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: proc_ctrl.cc,v 1.328 2010-04-02 21:22:17 sshwarts Exp $
|
||||
// $Id: proc_ctrl.cc,v 1.329 2010-04-03 05:59:07 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001-2010 The Bochs Project
|
||||
@ -561,7 +561,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)
|
||||
* limited to 40 bits.
|
||||
*/
|
||||
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE2)) { // Pentium 4 processor (see cpuid.cc)
|
||||
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE2)) { // Pentium 4 processor (see cpuid.cc)
|
||||
if ((ECX & 0x7fffffff) >= 18)
|
||||
exception(BX_GP_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: sse_move.cc,v 1.115 2010-03-30 18:12:18 sshwarts Exp $
|
||||
// $Id: sse_move.cc,v 1.116 2010-04-03 05:59:07 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003-2009 Stanislav Shwartsman
|
||||
@ -159,7 +159,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
|
||||
|
||||
BX_DEBUG(("FXSAVE: save FPU/MMX/SSE state"));
|
||||
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_MMX))
|
||||
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_MMX))
|
||||
{
|
||||
if(BX_CPU_THIS_PTR cr0.get_TS())
|
||||
exception(BX_NM_EXCEPTION, 0);
|
||||
@ -224,7 +224,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
|
||||
xmm.xmm32u(1) = (BX_CPU_THIS_PTR the_i387.fds);
|
||||
}
|
||||
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE)) {
|
||||
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE)) {
|
||||
xmm.xmm32u(2) = BX_MXCSR_REGISTER;
|
||||
xmm.xmm32u(3) = MXCSR_MASK;
|
||||
}
|
||||
@ -253,7 +253,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
|
||||
#endif
|
||||
|
||||
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE))
|
||||
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE))
|
||||
{
|
||||
/* store XMM register file */
|
||||
for(index=0; index < BX_XMM_REGISTERS; index++)
|
||||
@ -279,7 +279,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
|
||||
|
||||
BX_DEBUG(("FXRSTOR: restore FPU/MMX/SSE state"));
|
||||
|
||||
if (BX_CPU_SUPPORT_FEATURE(BX_CPU_MMX)) {
|
||||
if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_MMX)) {
|
||||
if(BX_CPU_THIS_PTR cr0.get_TS())
|
||||
exception(BX_NM_EXCEPTION, 0);
|
||||
|
||||
@ -329,7 +329,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
|
||||
BX_CPU_THIS_PTR the_i387.fds = xmm.xmm16u(2);
|
||||
}
|
||||
|
||||
if(/* BX_CPU_THIS_PTR cr4.get_OSFXSR() && */BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE))
|
||||
if(/* BX_CPU_THIS_PTR cr4.get_OSFXSR() && */BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE))
|
||||
{
|
||||
Bit32u new_mxcsr = xmm.xmm32u(2);
|
||||
if(new_mxcsr & ~MXCSR_MASK)
|
||||
@ -366,7 +366,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
|
||||
|
||||
/* If the OSFXSR bit in CR4 is not set, the FXRSTOR instruction does
|
||||
not restore the states of the XMM and MXCSR registers. */
|
||||
if(BX_CPU_THIS_PTR cr4.get_OSFXSR() && BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE))
|
||||
if(BX_CPU_THIS_PTR cr4.get_OSFXSR() && BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE))
|
||||
{
|
||||
/* load XMM register file */
|
||||
for(index=0; index < BX_XMM_REGISTERS; index++)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: vmx.h,v 1.22 2010-04-01 21:32:25 sshwarts Exp $
|
||||
// $Id: vmx.h,v 1.23 2010-04-03 05:59:07 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2009 Stanislav Shwartsman
|
||||
@ -932,8 +932,8 @@ enum VMX_Activity_State {
|
||||
((((Bit64u) VMX_MSR_CR4_FIXED0_HI) << 32) | VMX_MSR_CR4_FIXED0_LO)
|
||||
|
||||
// allowed 1-setting in CR0 in VMX mode
|
||||
#define VMX_MSR_CR4_FIXED1_LO GET32L(get_cr4_allow_mask(BX_CPU_THIS_PTR cpuid_features_bitmask))
|
||||
#define VMX_MSR_CR4_FIXED1_HI GET32H(get_cr4_allow_mask(BX_CPU_THIS_PTR cpuid_features_bitmask))
|
||||
#define VMX_MSR_CR4_FIXED1_LO GET32L(get_cr4_allow_mask(BX_CPU_THIS_PTR isa_extensions_bitmask))
|
||||
#define VMX_MSR_CR4_FIXED1_HI GET32H(get_cr4_allow_mask(BX_CPU_THIS_PTR isa_extensions_bitmask))
|
||||
|
||||
#define VMX_MSR_CR4_FIXED1 \
|
||||
((((Bit64u) VMX_MSR_CR4_FIXED1_HI) << 32) | VMX_MSR_CR4_FIXED1_LO)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user