mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

SSE optimization

Browse Source
This commit is contained in:
Stanislav Shwartsman 2010-12-19 07:06:40 +00:00
parent 48d94d6dc3
commit 4a85a8680e
6 changed files with 45 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.690 2010-12-18 11:58:16 sshwarts Exp $
// $Id: cpu.h,v 1.691 2010-12-19 07:06:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2010 The Bochs Project
@ -987,6 +987,9 @@ public: // for now...
#if BX_CPU_LEVEL >= 5
bx_bool ignore_bad_msrs;
#endif
#if BX_CPU_LEVEL >= 6
bx_bool sse_ok;
#endif
// for exceptions
jmp_buf jmp_buf_env;
@ -3154,6 +3157,9 @@ public: // for now...
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
BX_SMF void handleAlignmentCheck(void);
#endif
#if BX_CPU_LEVEL >= 6
BX_SMF void handleSseModeChange(void);
#endif
#if BX_CPU_LEVEL >= 5
BX_SMF bx_bool rdmsr(Bit32u index, Bit64u *val_64) BX_CPP_AttrRegparmN(2);
@ -3482,7 +3488,7 @@ BX_CPP_INLINE void BX_CPU_C::prepareMMX(void)
#if BX_CPU_LEVEL >= 6
BX_CPP_INLINE void BX_CPU_C::prepareSSE(void)
{
if(BX_CPU_THIS_PTR cr0.get_EM() || !BX_CPU_THIS_PTR cr4.get_OSFXSR())
if(! BX_CPU_THIS_PTR sse_ok)
exception(BX_UD_EXCEPTION, 0);
if(BX_CPU_THIS_PTR cr0.get_TS())

10
bochs/cpu/crregs.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: crregs.cc,v 1.22 2010-11-23 14:59:35 sshwarts Exp $
// $Id: crregs.cc,v 1.23 2010-12-19 07:06:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2010 Stanislav Shwartsman
@ -891,6 +891,10 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR0(bx_address val)
handleCpuModeChange();
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#endif
// Modification of PG,PE flushes TLB cache according to docs.
// Additionally, the TLB strategy is based on the current value of
// WP, so if that changes we must also flush the TLB.
@ -1067,6 +1071,10 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR4(bx_address val)
BX_CPU_THIS_PTR cr4.set32((Bit32u) val);
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#endif
return 1;
}
#endif // BX_CPU_LEVEL >= 4

6
bochs/cpu/init.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.247 2010-12-06 21:52:41 sshwarts Exp $
// $Id: init.cc,v 1.248 2010-12-19 07:06:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2009 The Bochs Project
@ -694,6 +694,9 @@ void BX_CPU_C::after_restore_state(void)
handleAlignmentCheck();
#endif
handleCpuModeChange();
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#endif
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_IA32_REAL) CPL = 0;
else {
@ -1024,6 +1027,7 @@ void BX_CPU_C::reset(unsigned source)
#if BX_CPU_LEVEL >= 6
// Reset XMM state - unchanged on #INIT
BX_CPU_THIS_PTR sse_ok = 0;
if (source == BX_RESET_HARDWARE) {
for(n=0; n<BX_XMM_REGISTERS; n++)
{

12
bochs/cpu/proc_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.338 2010-09-24 21:15:16 sshwarts Exp $
// $Id: proc_ctrl.cc,v 1.339 2010-12-19 07:06:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2010 The Bochs Project
@ -544,6 +544,16 @@ void BX_CPU_C::handleAlignmentCheck(void)
}
#endif
#if BX_CPU_LEVEL >= 6
void BX_CPU_C::handleSseModeChange(void)
{
if(BX_CPU_THIS_PTR cr0.get_EM() || !BX_CPU_THIS_PTR cr4.get_OSFXSR())
BX_CPU_THIS_PTR sse_ok = 0;
else
BX_CPU_THIS_PTR sse_ok = 1;
}
#endif
void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 5

10
bochs/cpu/smm.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: smm.cc,v 1.72 2010-04-29 19:34:32 sshwarts Exp $
// $Id: smm.cc,v 1.73 2010-12-19 07:06:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006-2009 Stanislav Shwartsman
@ -213,6 +213,10 @@ void BX_CPU_C::enter_system_management_mode(void)
handleAlignmentCheck();
#endif
#if BX_CPU_LEVEL >= 6
BX_CPU_THIS_PTR sse_ok = 0; // CR4 is cleared
#endif
/* DS (Data Segment) and descriptor cache */
parse_selector(0x0000,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector);
@ -650,6 +654,10 @@ bx_bool BX_CPU_C::smram_restore_state(const Bit32u *saved_state)
handleCpuModeChange();
#if BX_CPU_LEVEL >= 6
handleSseModeChange();
#endif
Bit16u ar_data = SMRAM_FIELD(saved_state, SMRAM_FIELD_LDTR_SELECTOR_AR) >> 16;
if (set_segment_ar_data(&BX_CPU_THIS_PTR ldtr,
(ar_data >> 8) & 1,

4
bochs/cpu/vmx.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vmx.cc,v 1.73 2010-11-12 20:46:59 sshwarts Exp $
// $Id: vmx.cc,v 1.74 2010-12-19 07:06:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2009-2010 Stanislav Shwartsman
@ -1583,6 +1583,7 @@ Bit32u BX_CPU_C::VMenterLoadCheckGuestState(Bit64u *qualification)
handleAlignmentCheck();
#endif
handleCpuModeChange();
handleSseModeChange();
return VMXERR_NO_ERROR;
}
@ -2027,6 +2028,7 @@ void BX_CPU_C::VMexitLoadHostState(void)
handleAlignmentCheck();
#endif
handleCpuModeChange();
handleSseModeChange();
}
void BX_CPU_C::VMexit(bxInstruction_c *i, Bit32u reason, Bit64u qualification)