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58 Commits

Author SHA1 Message Date
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction 
Set of minor fixes for correctness
 2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
8221fa6838 - Fixed zero upper 32-bit part of GPR in x86-64 mode 
- CMOV_GdEd should zero upper 32-bit part of GPR register even if the
    'cmov' condition was false !
 2007-01-26 22:12:05 +00:00
Stanislav Shwartsman
acd1a05f6f Fixed bugs for SSE3E execution and decoding 2007-01-25 21:44:35 +00:00
Stanislav Shwartsman
f8003098b1 Rename SSE4 to SSE3E to match intel docs. SSE4 coming later ;) 
Fixed "last prefix" for REX in 64-bit mode
 2007-01-25 19:09:41 +00:00
Stanislav Shwartsman
16713b309d PALIGNR fixed 2006-05-16 16:20:26 +00:00
Stanislav Shwartsman
03eac64013 Added decoding of new SSE4 instructions (recently published in Intel docs) 
At least CPUID detects them correctly
The code is never tested (still) ! (but should work fine)
 2006-04-06 18:30:05 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU 
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
 2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
0150904e9d Improve debug messages and optimize 2006-02-22 20:58:16 +00:00
Stanislav Shwartsman
5c58b22f44 Fixed opcode names according to Intel docs 
Fixed bug found during disasm validation
 2006-02-17 13:34:31 +00:00
Stanislav Shwartsman
d1c722211e Fix duplicate opcodes, fix opcode names and disasm bugs 2005-09-23 16:45:41 +00:00
Stanislav Shwartsman
3d9ee328fb PMOVMSKB and PEXTRW instruction should zero-extend dest when in 64-bit mode 2005-09-12 18:08:35 +00:00
Stanislav Shwartsman
80c895498e Fixed comments for code 2005-08-10 18:40:38 +00:00
Stanislav Shwartsman
a66b45e024 Fixed bug for masked writes in 64-bit mode 2005-08-10 18:34:00 +00:00
Stanislav Shwartsman
d10731f162 Update my e-mail in source files 
Update committed SF patches in changes
 2005-05-12 18:07:48 +00:00
Stanislav Shwartsman
3074078297 Added CVS version header to all the files. 
One more small change in APIC
 2005-03-19 20:44:01 +00:00
Stanislav Shwartsman
33b50ec4c4 For spammers o 2004-04-08 17:17:47 +00:00
Stanislav Shwartsman
1706beda30 fixed bug in floatx80_class function 
mmx code optimizations
 2004-03-03 21:09:08 +00:00
Stanislav Shwartsman
ecdbf40aac fixed compilation error for case when 3dnow! enabled and sse not 2004-01-31 17:13:05 +00:00
Stanislav Shwartsman
9120961241 update checking for pending FPU exceptions code 2004-01-31 13:43:26 +00:00
Stanislav Shwartsman
56beb4110c Little code optimization 2003-09-26 19:20:17 +00:00
Stanislav Shwartsman
1616539667 additional FPU changes 2003-08-01 09:32:33 +00:00
Stanislav Shwartsman
1d45167e5b Merged NEW-INSTRUCTIONS branch 2003-05-15 16:41:17 +00:00
Volker Ruppert
79b811f23f - fixed warnings in these files: 
cpu/fetchdecode.cc
  cpu/mmx.cc
  cpu/proc_ctrl.cc
  iodev/virt_timer.cc
  plugin.cc
 2003-05-02 12:22:48 +00:00
Stanislav Shwartsman
fa623fda74 FPU tag word is 16bit only 2003-04-25 18:43:48 +00:00
Stanislav Shwartsman
88d433bb73 Implemented MASKMOVQ 2003-04-23 18:57:57 +00:00
Stanislav Shwartsman
40bd4f138b Little style changes 
Elliminated i387_t alimit field (not used in FPU)
 2003-04-16 18:38:53 +00:00
Stanislav Shwartsman
aa9152129c Changes in i387 register file definition. Define common FPU/MMX register file. 2003-04-12 21:02:08 +00:00
Stanislav Shwartsman
216124c6c3 Send #MF exception for MMX instructions if there is a pending FPU exception 2003-04-05 12:49:14 +00:00
Stanislav Shwartsman
8193a710ad Changed MMX/SSE/SSE2 diagnostic messages to be more informative 2003-03-21 20:33:23 +00:00
Christophe Bothamy
50efc3b8c7 - apply Conn Clark's patch.perf-regparm-cclark : 
- it works only on x86 with gcc2.95+
  - uses the GCC function atribute "regparm(n)" to declare that certain
    functions use the register calling convention
  - performance improvement is about 6%
 2003-03-02 23:59:12 +00:00
Stanislav Shwartsman
513db033ab fixed compilation error and a logic bug together 2003-01-09 05:21:22 +00:00
Stanislav Shwartsman
e6eacd984f Implemented MOVD 64bit extensions 2003-01-08 20:33:28 +00:00
Stanislav Shwartsman
e1d5cddc6d Fixed a problem with zero-count shift in following instructions: 
PSRAW_PqQq    (MMX)
PSRAD_PqQq    (MMX)
PSRAW_PqIb    (MMX)
PSRAD_PqIb    (MMX)

PSRAW_VdqWdq  (SSE)
PSRAD_VdqWdq  (SSE)
PSRAW_PdqIb   (SSE)
PSRAD_PdqIb   (SSE)

When register was shifted by 0 bits the result produced was incorrect.

Now Bochs fully passes MMX test provided by
Hentai Yagi [hentai_yagi@yahoo.com.au] !
 2002-12-29 21:14:25 +00:00
Stanislav Shwartsman
8909ce442c Fixed problem in PSRLD_PqIb instruction 2002-12-28 20:18:56 +00:00
Stanislav Shwartsman
6ccd2fb7fa Fixed bug in following MMX instructions: 
void BX_CPU_C::PUNPCKLBW_PqQd(bxInstruction_c *i)
void BX_CPU_C::PUNPCKLWD_PqQd(bxInstruction_c *i)
void BX_CPU_C::PUNPCKLDQ_PqQd(bxInstruction_c *i)

Thanks to Hentai Yagi [hentai_yagi@yahoo.com.au]
that provided nessesary test application.
 2002-12-28 19:06:29 +00:00
Stanislav Shwartsman
04c7d9301b implemented 
PINSRW_VdqEdIb
PEXTRW_VdqEdIb
PINSRW_PqEdIb
PEXTRW_PqEdIb

instructions
 2002-12-02 21:24:09 +00:00
Stanislav Shwartsman
57fd94744d Implemented MOVQ2DQ/MOVDQ2Q instructions 
Small fixes with MMX environment
 2002-11-30 14:42:41 +00:00
Bryce Denney
9b14101a05 - rewrite typecast of temp to Bit64u to keep VC++ happy. I don't really 
know what it thought was wrong.
 2002-11-19 05:53:47 +00:00
Stanislav Shwartsman
3217759a75 Implemented 
PSHUFLW_VqWqIb, PSHUFHW_VqWqIb instructions
 2002-11-15 17:34:47 +00:00
Stanislav Shwartsman
da8a2a71b1 Fixed bug PSHUFW instruction 2002-11-15 17:02:06 +00:00
Stanislav Shwartsman
62e362afc2 just typo 2002-11-15 15:55:36 +00:00
Stanislav Shwartsman
34dd74fe6c Fixed BUG in PMADDWD instruction 2002-11-15 15:51:12 +00:00
Stanislav Shwartsman
65b8712d04 More tuning of SSE 2002-11-14 19:59:29 +00:00
Stanislav Shwartsman
5803e20240 Changed policy of SSE/SSE2 checking 2002-11-13 21:00:05 +00:00
Stanislav Shwartsman
0df9c9af85 Implemented integer SSE2 instructions: 
PSRLW_PdqIb
PSRLD_PdqIb
PSRLQ_PdqIb
PSLLW_PdqIb
PSLLD_PdqIb
PSLLQ_PdqIb
PSRAW_PdqIb
PSRAD_PdqIb
PSRLW_VdqWdq
PSRLD_VdqWdq
PSRLQ_VdqWdq
PSRAW_PdqWdq
PSRAD_PdqWdq
PSLLW_VdqWdq
PSLLD_VdqWdq
PSLLQ_VdqWdq
PMOVMSKB_GdVRdq
PMULUDQ_VdqWdq
PMINUB_VdqWdq
PMINSW_VdqWdq
PMAXUB_VdqWdq
PMAXSW_VdqWdq

Fixed bug in the PMINUB_PqQq and PMAXUB_PqQq SSE instructions
 2002-11-08 17:47:46 +00:00
Stanislav Shwartsman
4363745725 Implemented SSE2 integer instructions: 
PACKSSDW_VdqWdq
PUNPCKHDQ_VdqWq
PUNPCKHWD_VdqWq
PUNPCKHBW_VdqWq
PUNPCKHQDQ_VdqWq
MOVD_EdVd
MOVD_VdqEd
 2002-11-08 12:47:24 +00:00
Stanislav Shwartsman
b200ff2058 Implemented several integer SSE2 instructions (similar to the MMX): 
PACKSSWB_VdqWq
PCMPGTB_VdqWq
PCMPGTW_VdqWq
PCMPGTD_VdqWdq
PACKUSWB_VdqWdq
PCMPEQB_VdqWdq
PCMPEQW_VdqWdq
PCMPEQD_VdqWdq
PADDQ_VdqWdq
PSUBUSB_VdqWdq
PSUBUSW_VdqWdq
PAND_VdqWdq
PANDN_VdqWdq
PAVGB_VdqWdq
PAVGW_VdqWdq
POR_VdqWdq
PXOR_VdqWdq
PSUBB_VdqWdq
PSUBW_VdqWdq
PSUBD_VdqWdq
PSUBQ_VdqWdq
PADDB_VdqWdq
PADDW_VdqWdq
PADDD_VdqWdq
PADDQ_VdqWdq
 2002-11-07 22:41:34 +00:00
Stanislav Shwartsman
0e60aa8232 We will need integer saturation functions also in SSE2 instructions 2002-11-02 12:35:33 +00:00
Stanislav Shwartsman
277f14dd76 Implemented PMOVMSKB_GdPRq instruction (SSE) 2002-10-19 21:46:07 +00:00
Stanislav Shwartsman
63ac78d496 Implemented MOVNTQ instruction 2002-10-19 21:28:50 +00:00