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234 Commits

Author SHA1 Message Date
Stanislav Shwartsman
ab6230a9a8 Implemented XSAVEC instruction emulation and XINUSE optimization in the XSAVEOPT instruction 2014-03-17 20:29:44 +00:00
Stanislav Shwartsman
550e6bd307 moved (c) to year 2014 for few files 2014-02-06 17:06:25 +00:00
Stanislav Shwartsman
aea9ae1976 added definitions (CPUID bit, VMX fields and VMXEXIT reasons, etc) from recently published Intel SDM rev049 2014-02-06 17:05:20 +00:00
Stanislav Shwartsman
36ba25847f Implemented last missed AVX-512 unsigned convert instructions 
The only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.WIG 21 VPMOVSXBD
512.66.0F38.WIG 22 VPMOVSXBQ
512.66.0F38.WIG 23 VPMOVSXWD
512.66.0F38.WIG 24 VPMOVSXWQ
512.66.0F38.W0  25 VPMOVSXDQ

512.66.0F38.WIG 31 VPMOVSZBD
512.66.0F38.WIG 32 VPMOVSZBQ
512.66.0F38.WIG 33 VPMOVSZWD
512.66.0F38.WIG 34 VPMOVSZWQ
512.66.0F38.W0  35 VPMOVSzDQ

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
 512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
 NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
 512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
 NDS.LIG.66.0F38.W1 4F VRSQRT14SD

NDS.512.66.0F3A.W0 03 VALIGND
NDS.512.66.0F3A.W1 03 VALIGNQ

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 19 VEXTRACTF32x4
512.66.0F3A.W1 1B VEXTRACTF64x4
512.66.0F3A.W0 39 VEXTRACTI32x4
512.66.0F3A.W1 3B VEXTRACTI64x4

512.66.0F3A.W0 26 VGETMANTPS
 512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
 NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-01-28 12:57:38 +00:00
Stanislav Shwartsman
c3b666d4ed fixed zmm reg name in disasm 2013-11-29 20:49:20 +00:00
Stanislav Shwartsman
940c2a1c8e fixes for disasm 2013-10-15 17:19:18 +00:00
Stanislav Shwartsman
9fb7384e6b finish sse tables cleanup in disasm and fetchdecode 2013-10-11 20:09:51 +00:00
Stanislav Shwartsman
582bf84bae apply same optimization to disasm as well 2013-10-10 21:00:26 +00:00
Stanislav Shwartsman
37a3a76cbb optimize old disasm code 2013-10-07 19:23:19 +00:00
Stanislav Shwartsman
d68a7ca953 add option to skip mem datasize printing in disasm 2013-10-07 19:12:12 +00:00
Stanislav Shwartsman
cb0eee9456 disasm fixes 2013-10-07 19:02:53 +00:00
Stanislav Shwartsman
059769e2a6 disasm bug fixes 2013-10-06 20:42:13 +00:00
Stanislav Shwartsman
e55611df21 disasm fixes 2013-10-06 19:04:52 +00:00
Stanislav Shwartsman
add8eea761 disasm bug fixes 2013-10-06 18:37:56 +00:00
Stanislav Shwartsman
fd370a4d41 fixes in disasm, added example of using bxInstruction_c disasm into dbg_main.cc (commented out for now) 2013-10-05 19:32:09 +00:00
Stanislav Shwartsman
d4bfbffdbb disasm fixes 2013-10-05 08:34:09 +00:00
Stanislav Shwartsman
5842d09434 rename call_far and ret_far opcodes to converge between two disasm modules 2013-10-04 17:47:52 +00:00
Stanislav Shwartsman
85b0402668 fixes for disasm 2013-10-02 19:23:34 +00:00
Stanislav Shwartsman
5331e8d4d3 rename disasm variable 2013-10-01 20:12:28 +00:00
Stanislav Shwartsman
2526282ed9 small additions for avx512 2013-09-20 18:27:33 +00:00
Stanislav Shwartsman
7297323c69 First step of AVX512 support implementation (simplest) 
decode and implement KMASK manipulation instructions
disasm: coming soon
 2013-09-08 19:19:16 +00:00
Stanislav Shwartsman
25f99f76c3 remove test registers from disasm as well 2013-08-23 05:54:51 +00:00
Stanislav Shwartsman
852b5c3749 implemented SHA new instructions announced in recent Intel SDM extensions document rev015 2013-07-24 18:44:22 +00:00
Stanislav Shwartsman
2638c1136a Add RDRAND/RDSEED instructions support (+ disasm) 
Of course no true random numbers will be generated - use standard "C" rand() function as stub.
In future it will be possible to improve (using another random generator) or even use real rdrand/rdseed intrinsics
 2012-10-09 15:16:48 +00:00
Stanislav Shwartsman
dbb23aed43 close another SMC hole 2012-10-01 18:19:09 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
df90b80352 set of small cpu fixes 2012-08-09 13:11:25 +00:00
Stanislav Shwartsman
be76f38b46 correct MOVBE decoding with prefix 0x66, also correct ADX decoding 2012-08-08 20:11:27 +00:00
Volker Ruppert
53438e92c6 - fixes based on Debian patches by Guillem Jover 
- set SHELL variable with configure script
  - add '--tag CXX' argument to libtool calls
 2012-07-14 07:01:43 +00:00
Stanislav Shwartsman
5d66e8450e implemented ADCX/ADOX instructions from rev013 of arch extensions published by Intel 2012-07-12 14:51:54 +00:00
Stanislav Shwartsman
bb7a648d91 Major commit ! 
------------

Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.

! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.

Some CPUID modules rework done to enable Toliman configuration.

Ckean up 'executable' attribute from all CPU source files.
 2012-02-13 23:29:01 +00:00
Stanislav Shwartsman
abda3a967c added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
06e88c4984 fixed uninitialized var 2011-11-26 18:38:43 +00:00
Stanislav Shwartsman
62b811e48f disasm: correctly handle VEX and XOP based opcodes 2011-11-23 19:43:50 +00:00
Stanislav Shwartsman
7158cf7228 fixed xop opcodes disasm tables 2011-11-23 16:44:38 +00:00
Stanislav Shwartsman
9be8552b80 - Implemented VM Functions support and EPTP-Switching VM Functions 
- Added VMEXIT conditions for INVPCID instruction

Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
 2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
42a0a178eb disasm for XOP instructions 2011-10-30 08:58:49 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions. 
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
 2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
aad57310c2 disasm for FMA4, better dbg print SSE rounding control with MXCSR 2011-10-06 20:33:10 +00:00
Stanislav Shwartsman
e3dae7adb1 added disasm for avx fma instructions 2011-09-29 19:50:27 +00:00
Stanislav Shwartsman
8c7a60b3cb fixed typo in sse4a disasm 2011-09-20 15:15:02 +00:00
Stanislav Shwartsman
50207eeb90 - Added support for AMD SSE4A emulation, the instructions can be enabled 
using .bochsrc CPUID option.
 2011-09-18 16:18:22 +00:00
Stanislav Shwartsman
e2f0880f1c support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
3f230d115e clean disasm opcodes.inc 2011-09-13 20:43:15 +00:00
Stanislav Shwartsman
cf56ffb6e0 BSF/BSR should stay, only F3 prefix change opcode 2011-08-31 21:13:50 +00:00
Stanislav Shwartsman
1f5e036695 lzcnt/tzcnt bmi instructions implemented 2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
9693bacacb syscall/sysret in legacy mode is supported in k6-2. preparing code to it ... 2011-08-30 20:41:00 +00:00
Stanislav Shwartsman
1328861175 typo fix 2011-08-28 21:41:54 +00:00
Stanislav Shwartsman
1dc8f56f06 disasm for AVX2 gather 2011-08-28 21:38:53 +00:00