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49 Commits

Author SHA1 Message Date
Stanislav Shwartsman
f791802286 infrastructure change for several AVX handlers to support any VL and only 128/256 2013-09-21 20:40:57 +00:00
Stanislav Shwartsman
cd55ace8c8 fixed compilation err, rename opcode and handler functions for PUSHA/POPA instructions 2013-09-21 10:03:49 +00:00
Stanislav Shwartsman
3803ac7fbe fixed evex override mscsr controls 2013-09-19 21:38:25 +00:00
Stanislav Shwartsman
d169860f6c added masked operations to simd_pfp.h, optimize simd_int.h, rewrite dpps instr using new masked op from simd_pfp.h 2013-09-17 20:49:26 +00:00
Stanislav Shwartsman
aa25c1db6a name convention change - search and replace 2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
1cebe5f83d rellback part of commit with xmm register access interface changes - doesn't work for big endian hosts 2013-09-16 19:10:42 +00:00
Stanislav Shwartsman
0cb0acc30f added evex decode tables - next step to populate them :) 2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
5d61c19b0b evex support - step2 2013-08-27 20:47:24 +00:00
Stanislav Shwartsman
2dbe81db51 first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel 2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions. 
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
 2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
 2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
9fbf7d2f15 small cleanups 2011-05-04 05:53:17 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
f705cbbc63 rename functions 2010-12-25 19:34:43 +00:00
Stanislav Shwartsman
c005444d5b split more SSE opcodes 2010-12-25 07:59:15 +00:00
Stanislav Shwartsman
040a8e1a3a split bunch of SSE opcodes 2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
709059ddcc integrate misaligned SSE into code 2010-12-22 21:24:19 +00:00
Stanislav Shwartsman
9ed116ada7 avoid similar issues (like it was in mmx.cc) in future 2010-09-26 20:35:24 +00:00
Stanislav Shwartsman
033a20b3b2 allow to configure CPU features at runtime - implemened on example of SSE/AES/MOVBE/POPCNT 2010-02-25 22:04:31 +00:00
Stanislav Shwartsman
7254ea36a1 copyright fixes + small optimization 2009-10-14 20:45:29 +00:00
Stanislav Shwartsman
e15bfef9f7 remove --enable-daz option, it will be turned on by default iff SSE2 is supported (like in real hardware) 2009-07-08 14:02:42 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
420f30816d inline integer saturation code - speedup for MMX/SSE integer 2008-04-06 13:56:22 +00:00
Stanislav Shwartsman
b929a2b2b8 Fixed minor issues - compilation and not only 2008-02-13 17:06:44 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
83f6eb6945 Changes copyrights for the files I wrote :) 
Also split EqId G1 group for x86-64
 2007-11-17 23:28:33 +00:00
Stanislav Shwartsman
58a2595bca Misaligned SSE support 2007-07-15 19:03:39 +00:00
Stanislav Shwartsman
5189cfbf10 SSE4 support 2007-04-19 16:12:21 +00:00
Stanislav Shwartsman
26f08fdb2c Change my e-mail to #SF one 2007-03-23 21:27:13 +00:00
Stanislav Shwartsman
a010cfb8ca Fix amount of XMM registers in non-x86-64 mode 2006-05-22 21:17:27 +00:00
Volker Ruppert
5e75dc3a10 - some more warnings in MSVC fixed 2005-06-06 20:14:50 +00:00
Stanislav Shwartsman
d10731f162 Update my e-mail in source files 
Update committed SF patches in changes
 2005-05-12 18:07:48 +00:00
Stanislav Shwartsman
3074078297 Added CVS version header to all the files. 
One more small change in APIC
 2005-03-19 20:44:01 +00:00
Stanislav Shwartsman
33b50ec4c4 For spammers o 2004-04-08 17:17:47 +00:00
Stanislav Shwartsman
cc7b85ae7e just update release dates 2004-02-13 21:27:45 +00:00
Stanislav Shwartsman
b17671f5ef Fixed compilation error 2003-11-19 20:57:13 +00:00
Stanislav Shwartsman
a6c1bdbbb2 Optimization of RCPSS/RCPPS functions 2003-11-19 20:27:58 +00:00
Stanislav Shwartsman
ac20b6405a - FXSAVE/FXRSTOR instructions should be available in P6 mode 
- Added second UD2 opcode to fetchdecode
- Added RDPMC instruction to fetchdecode
- 'changes' updated
 2003-10-24 18:34:16 +00:00
Stanislav Shwartsman
04ebd29f92 dos2unix fix 2003-05-19 15:02:47 +00:00
Stanislav Shwartsman
1d45167e5b Merged NEW-INSTRUCTIONS branch 2003-05-15 16:41:17 +00:00
Christophe Bothamy
50efc3b8c7 - apply Conn Clark's patch.perf-regparm-cclark : 
- it works only on x86 with gcc2.95+
  - uses the GCC function atribute "regparm(n)" to declare that certain
    functions use the register calling convention
  - performance improvement is about 6%
 2003-03-02 23:59:12 +00:00
Stanislav Shwartsman
5222261080 Save/Restore FPU TOP-OF-STACK in FXSAVE/FXRSTOR instructions 2003-01-23 18:33:35 +00:00
Christophe Bothamy
ff89875ffd - remove unused (seems to be) typedef 2002-12-12 13:26:29 +00:00
Stanislav Shwartsman
a4806d3fce Fixed the MXCSR mask value 2002-11-22 21:42:46 +00:00
Stanislav Shwartsman
b200ff2058 Implemented several integer SSE2 instructions (similar to the MMX): 
PACKSSWB_VdqWq
PCMPGTB_VdqWq
PCMPGTW_VdqWq
PCMPGTD_VdqWdq
PACKUSWB_VdqWdq
PCMPEQB_VdqWdq
PCMPEQW_VdqWdq
PCMPEQD_VdqWdq
PADDQ_VdqWdq
PSUBUSB_VdqWdq
PSUBUSW_VdqWdq
PAND_VdqWdq
PANDN_VdqWdq
PAVGB_VdqWdq
PAVGW_VdqWdq
POR_VdqWdq
PXOR_VdqWdq
PSUBB_VdqWdq
PSUBW_VdqWdq
PSUBD_VdqWdq
PSUBQ_VdqWdq
PADDB_VdqWdq
PADDW_VdqWdq
PADDD_VdqWdq
PADDQ_VdqWdq
 2002-11-07 22:41:34 +00:00
Stanislav Shwartsman
0e60aa8232 We will need integer saturation functions also in SSE2 instructions 2002-11-02 12:35:33 +00:00
Stanislav Shwartsman
22d292d83f Detalized XMM register definition for BIG/LITTLE endian systems 2002-11-02 12:09:27 +00:00
Stanislav Shwartsman
194952a53d Merged BOCHS-SSE branch 2002-10-16 17:37:35 +00:00