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Merged BOCHS-SSE branch

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This commit is contained in:
Stanislav Shwartsman 2002-10-16 17:37:35 +00:00
parent 7313a837d4
commit 194952a53d
15 changed files with 7697 additions and 6925 deletions
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6492
bochs/configure vendored
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File diff suppressed because it is too large Load Diff

2
bochs/cpu/Makefile.in
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@ -60,6 +60,8 @@ OBJS = \
ctrl_xfer32.o \
ctrl_xfer16.o \
mmx.o \
sse.o \
sse2.o \
soft_int.o \
io_pro.o \
$(APIC_OBJS) \

259
bochs/cpu/cpu.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.103 2002-10-13 22:38:17 bdenney Exp $
// $Id: cpu.h,v 1.104 2002-10-16 17:37:33 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1281,6 +1281,10 @@ class BX_MEM_C;
#include "cpu/i387.h"
#if BX_SUPPORT_SSE || BX_SUPPORT_SSE2
#include "cpu/xmm.h"
#endif
class BX_CPU_C : public logfunctions {
public: // for now...
@ -1415,6 +1419,11 @@ union {
i387_t the_i387;
#if BX_SUPPORT_SSE || BX_SUPPORT_SSE2
bx_xmm_reg_t xmm[BX_XMM_REGISTERS];
bx_mxcsr_t mxcsr;
#endif
// pointer to the address space that this processor uses.
BX_MEM_C *mem;
@ -2029,11 +2038,232 @@ union {
BX_SMF void PSLLQ_PqIb(bxInstruction_c *i);
/* MMX */
#if BX_SUPPORT_MMX
BX_SMF void PrepareMmxInstruction(void);
BX_SMF void PrintMmxRegisters(void);
#if BX_SUPPORT_MMX || BX_SUPPORT_SSE || BX_SUPPORT_SSE2
BX_SMF void prepareMMX(void);
BX_SMF void printMmxRegisters(void);
#endif
#if BX_SUPPORT_SSE || BX_SUPPORT_SSE2
BX_SMF void prepareSSE(void);
#endif
/* SSE */
BX_SMF void FXSAVE(bxInstruction_c *i);
BX_SMF void FXRSTOR(bxInstruction_c *i);
BX_SMF void LDMXCSR(bxInstruction_c *i);
BX_SMF void STMXCSR(bxInstruction_c *i);
BX_SMF void PREFETCH(bxInstruction_c *i);
/* SSE */
/* SSE */
BX_SMF void MOVUPS_VpsWps(bxInstruction_c *i);
BX_SMF void MOVSS_VssWss(bxInstruction_c *i);
BX_SMF void MOVUPS_WpsVps(bxInstruction_c *i);
BX_SMF void MOVSS_WssVss(bxInstruction_c *i);
BX_SMF void MOVLPS_VpsMq(bxInstruction_c *i);
BX_SMF void MOVLPS_MqVps(bxInstruction_c *i);
BX_SMF void UNPCKLPS_VpsWq(bxInstruction_c *i);
BX_SMF void UNPCKHPS_VpsWq(bxInstruction_c *i);
BX_SMF void MOVHPS_VpsMq(bxInstruction_c *i);
BX_SMF void MOVHPS_MqVps(bxInstruction_c *i);
BX_SMF void MOVAPS_VpsWps(bxInstruction_c *i);
BX_SMF void MOVAPS_WpsVps(bxInstruction_c *i);
BX_SMF void CVTPI2PS_VpsQq(bxInstruction_c *i);
BX_SMF void CVTSI2SS_VssEd(bxInstruction_c *i);
BX_SMF void MOVNTPS_MdqVps(bxInstruction_c *i);
BX_SMF void CVTTPS2PI_PqWps(bxInstruction_c *i);
BX_SMF void CVTTSS2SI_GdWss(bxInstruction_c *i);
BX_SMF void CVTPS2PI_PqWps(bxInstruction_c *i);
BX_SMF void CVTSS2SI_GdWss(bxInstruction_c *i);
BX_SMF void UCOMISS_VssWss(bxInstruction_c *i);
BX_SMF void COMISS_VpsWps(bxInstruction_c *i);
BX_SMF void MOVMSKPS_GdVRps(bxInstruction_c *i);
BX_SMF void SQRTPS_VpsWps(bxInstruction_c *i);
BX_SMF void SQRTSS_VssWss(bxInstruction_c *i);
BX_SMF void RSQRTPS_VpsWps(bxInstruction_c *i);
BX_SMF void RSQRTSS_VssWss(bxInstruction_c *i);
BX_SMF void RCPPS_VpsWps(bxInstruction_c *i);
BX_SMF void RCPSS_VssWss(bxInstruction_c *i);
BX_SMF void ANDPS_VpsWps(bxInstruction_c *i);
BX_SMF void ANDNPS_VpsWps(bxInstruction_c *i);
BX_SMF void ORPS_VpsWps(bxInstruction_c *i);
BX_SMF void XORPS_VpsWps(bxInstruction_c *i);
BX_SMF void ADDPS_VpsWps(bxInstruction_c *i);
BX_SMF void ADDSS_VssWss(bxInstruction_c *i);
BX_SMF void MULPS_VpsWps(bxInstruction_c *i);
BX_SMF void MULSS_VssWss(bxInstruction_c *i);
BX_SMF void SUBPS_VpsWps(bxInstruction_c *i);
BX_SMF void SUBSS_VssWss(bxInstruction_c *i);
BX_SMF void MINPS_VpsWps(bxInstruction_c *i);
BX_SMF void MINSS_VssWss(bxInstruction_c *i);
BX_SMF void DIVPS_VpsWps(bxInstruction_c *i);
BX_SMF void DIVSS_VssWss(bxInstruction_c *i);
BX_SMF void MAXPS_VpsWps(bxInstruction_c *i);
BX_SMF void MAXSS_VssWss(bxInstruction_c *i);
BX_SMF void PSHUFW_PqQqIb(bxInstruction_c *i);
BX_SMF void PSHUFLW_VqWqIb(bxInstruction_c *i);
BX_SMF void CMPPS_VpsWpsIb(bxInstruction_c *i);
BX_SMF void CMPSS_VssWssIb(bxInstruction_c *i);
BX_SMF void PINSRW_PqEdIb(bxInstruction_c *i);
BX_SMF void PEXTRW_PqEdIb(bxInstruction_c *i);
BX_SMF void SHUFPS_VpsWpsIb(bxInstruction_c *i);
BX_SMF void PMOVMSKB_GdPRq(bxInstruction_c *i);
BX_SMF void PMINUB_PqQq(bxInstruction_c *i);
BX_SMF void PMAXUB_PqQq(bxInstruction_c *i);
BX_SMF void PAVGB_PqQq(bxInstruction_c *i);
BX_SMF void PAVGW_PqQq(bxInstruction_c *i);
BX_SMF void PMULHUW_PqQq(bxInstruction_c *i);
BX_SMF void MOVNTQ_MqPq(bxInstruction_c *i);
BX_SMF void PMINSW_PqQq(bxInstruction_c *i);
BX_SMF void PMAXSW_PqQq(bxInstruction_c *i);
BX_SMF void PSADBW_PqQq(bxInstruction_c *i);
BX_SMF void MASKMOVQ_PqPRq(bxInstruction_c *i);
/* SSE */
/* SSE2 */
BX_SMF void MOVUPD_VpdWpd(bxInstruction_c *i);
BX_SMF void MOVSD_VsdWsd(bxInstruction_c *i);
BX_SMF void MOVUPD_WpdVpd(bxInstruction_c *i);
BX_SMF void MOVSD_WsdVsd(bxInstruction_c *i);
BX_SMF void MOVLPD_VsdMq(bxInstruction_c *i);
BX_SMF void MOVLPD_MqVsd(bxInstruction_c *i);
BX_SMF void UNPCKLPD_VpdWq(bxInstruction_c *i);
BX_SMF void UNPCKHPD_VpdWq(bxInstruction_c *i);
BX_SMF void MOVHPD_VpdMq(bxInstruction_c *i);
BX_SMF void MOVHPD_MqVpd(bxInstruction_c *i);
BX_SMF void MOVAPD_VpdWpd(bxInstruction_c *i);
BX_SMF void MOVAPD_WpdVpd(bxInstruction_c *i);
BX_SMF void CVTPI2PD_VpdQd(bxInstruction_c *i);
BX_SMF void CVTSI2SD_VsdEd(bxInstruction_c *i);
BX_SMF void MOVNTPD_MdqVpd(bxInstruction_c *i);
BX_SMF void CVTTPD2PI_PqWpd(bxInstruction_c *i);
BX_SMF void CVTTSD2SI_GdWsd(bxInstruction_c *i);
BX_SMF void CVTPD2PI_PqWpd(bxInstruction_c *i);
BX_SMF void CVTSD2SI_GdWsd(bxInstruction_c *i);
BX_SMF void UCOMISD_VsdWsd(bxInstruction_c *i);
BX_SMF void COMISD_VpdWpd(bxInstruction_c *i);
BX_SMF void MOVMSKPD_EdVRpd(bxInstruction_c *i);
BX_SMF void SQRTPD_VpdWpd(bxInstruction_c *i);
BX_SMF void SQRTSD_VsdWsd(bxInstruction_c *i);
BX_SMF void ANDPD_VpdWpd(bxInstruction_c *i);
BX_SMF void ANDNPD_VpdWpd(bxInstruction_c *i);
BX_SMF void ORPD_VpdWpd(bxInstruction_c *i);
BX_SMF void XORPD_VpdWpd(bxInstruction_c *i);
BX_SMF void ADDPD_VpdWpd(bxInstruction_c *i);
BX_SMF void ADDSD_VsdWsd(bxInstruction_c *i);
BX_SMF void MULPD_VpdWpd(bxInstruction_c *i);
BX_SMF void MULSD_VsdWsd(bxInstruction_c *i);
BX_SMF void CVTPS2PD_VpsWps(bxInstruction_c *i);
BX_SMF void CVTPD2PS_VpdWpd(bxInstruction_c *i);
BX_SMF void CVTSD2SS_VsdWsd(bxInstruction_c *i);
BX_SMF void CVTSS2SD_VssWss(bxInstruction_c *i);
BX_SMF void CVTDQ2PS_VpsWdq(bxInstruction_c *i);
BX_SMF void CVTPS2DQ_VdqWps(bxInstruction_c *i);
BX_SMF void CVTTPS2DQ_VdqWps(bxInstruction_c *i);
BX_SMF void SUBPD_VpdWpd(bxInstruction_c *i);
BX_SMF void SUBSD_VsdWsd(bxInstruction_c *i);
BX_SMF void MINPD_VpdWpd(bxInstruction_c *i);
BX_SMF void MINSD_VsdWsd(bxInstruction_c *i);
BX_SMF void DIVPD_VpdWpd(bxInstruction_c *i);
BX_SMF void DIVSD_VsdWsd(bxInstruction_c *i);
BX_SMF void MAXPD_VpdWpd(bxInstruction_c *i);
BX_SMF void MAXSD_VsdWsd(bxInstruction_c *i);
BX_SMF void PUNPCKLBW_VdqWq(bxInstruction_c *i);
BX_SMF void PUNPCKLWD_VdqWq(bxInstruction_c *i);
BX_SMF void PUNPCKLDQ_VdqWq(bxInstruction_c *i);
BX_SMF void PACKSSWB_VdqWq(bxInstruction_c *i);
BX_SMF void PCMPGTB_VdqWq(bxInstruction_c *i);
BX_SMF void PCMPGTW_VdqWq(bxInstruction_c *i);
BX_SMF void PCMPGTD_VdqWdq(bxInstruction_c *i);
BX_SMF void PACKUSWB_VdqWdq(bxInstruction_c *i);
BX_SMF void PUNPCKHBW_VdqWq(bxInstruction_c *i);
BX_SMF void PUNPCKHWD_VdqWq(bxInstruction_c *i);
BX_SMF void PUNPCKHDQ_VdqWq(bxInstruction_c *i);
BX_SMF void PACKSSDW_VdqWdq(bxInstruction_c *i);
BX_SMF void PUNPCKLQDQ_VdqWq(bxInstruction_c *i);
BX_SMF void PUNPCKHQDQ_VdqWq(bxInstruction_c *i);
BX_SMF void MOVD_VdqEd(bxInstruction_c *i);
BX_SMF void MOVDQA_VdqWdq(bxInstruction_c *i);
BX_SMF void MOVDQU_VdqWdq(bxInstruction_c *i);
BX_SMF void PSHUFD_VdqWdqIb(bxInstruction_c *i);
BX_SMF void PSHUFHW_VqWqIb(bxInstruction_c *i);
BX_SMF void PCMPEQB_VdqWdq(bxInstruction_c *i);
BX_SMF void PCMPEQW_VdqWdq(bxInstruction_c *i);
BX_SMF void PCMPEQD_VdqWdq(bxInstruction_c *i);
BX_SMF void MOVD_EdVd(bxInstruction_c *i);
BX_SMF void MOVD_VqWq(bxInstruction_c *i);
BX_SMF void MOVDQA_WdqVdq(bxInstruction_c *i);
BX_SMF void MOVDQU_WdqVdq(bxInstruction_c *i);
BX_SMF void CMPPD_VpdWpdIb(bxInstruction_c *i);
BX_SMF void CMPSD_VsdWsdIb(bxInstruction_c *i);
BX_SMF void MOVNTI_MdGd(bxInstruction_c *i);
BX_SMF void PINSRW_VdqEdIb(bxInstruction_c *i);
BX_SMF void PEXTRW_VdqEdIb(bxInstruction_c *i);
BX_SMF void SHUFPD_VpdWpdIb(bxInstruction_c *i);
BX_SMF void PSRLW_VdqWdq(bxInstruction_c *i);
BX_SMF void PSRLD_VdqWdq(bxInstruction_c *i);
BX_SMF void PSRLQ_VdqWdq(bxInstruction_c *i);
BX_SMF void PADDQ_PqQq(bxInstruction_c *i);
BX_SMF void PADDQ_VdqWdq(bxInstruction_c *i);
BX_SMF void PMULLW_VdqWdq(bxInstruction_c *i);
BX_SMF void MOVQ_WqVq(bxInstruction_c *i);
BX_SMF void MOVDQ2Q_PqVRq(bxInstruction_c *i);
BX_SMF void MOVQ2DQ_VdqQq(bxInstruction_c *i);
BX_SMF void PMOVMSKB_GdVRdq(bxInstruction_c *i);
BX_SMF void PSUBUSB_VdqWdq(bxInstruction_c *i);
BX_SMF void PSUBUSW_VdqWdq(bxInstruction_c *i);
BX_SMF void PMINUB_VdqWdq(bxInstruction_c *i);
BX_SMF void PAND_VdqWdq(bxInstruction_c *i);
BX_SMF void PADDUSB_VdqWdq(bxInstruction_c *i);
BX_SMF void PADDUSW_VdqWdq(bxInstruction_c *i);
BX_SMF void PMAXUB_VdqWdq(bxInstruction_c *i);
BX_SMF void PANDN_VdqWdq(bxInstruction_c *i);
BX_SMF void PAVGB_VdqWdq(bxInstruction_c *i);
BX_SMF void PSRAW_VdqWdq(bxInstruction_c *i);
BX_SMF void PSRAD_VdqWdq(bxInstruction_c *i);
BX_SMF void PAVGW_VdqWdq(bxInstruction_c *i);
BX_SMF void PMULHUW_VdqWdq(bxInstruction_c *i);
BX_SMF void PMULHW_VdqWdq(bxInstruction_c *i);
BX_SMF void CVTTPD2DQ_VqWpd(bxInstruction_c *i);
BX_SMF void CVTPD2DQ_VqWpd(bxInstruction_c *i);
BX_SMF void CVTDQ2PD_VpdWq(bxInstruction_c *i);
BX_SMF void MOVNTDQ_MdqVdq(bxInstruction_c *i);
BX_SMF void PSUBSB_VdqWdq(bxInstruction_c *i);
BX_SMF void PSUBSW_VdqWdq(bxInstruction_c *i);
BX_SMF void PMINSW_VdqWdq(bxInstruction_c *i);
BX_SMF void POR_VdqWdq(bxInstruction_c *i);
BX_SMF void PADDSB_VdqWdq(bxInstruction_c *i);
BX_SMF void PADDSW_VdqWdq(bxInstruction_c *i);
BX_SMF void PMAXSW_VdqWdq(bxInstruction_c *i);
BX_SMF void PXOR_VdqWdq(bxInstruction_c *i);
BX_SMF void PSLLW_VdqWdq(bxInstruction_c *i);
BX_SMF void PSLLD_VdqWdq(bxInstruction_c *i);
BX_SMF void PSLLQ_VdqWdq(bxInstruction_c *i);
BX_SMF void PMULUDQ_PqQq(bxInstruction_c *i);
BX_SMF void PMULUDQ_VdqWdq(bxInstruction_c *i);
BX_SMF void PMADDWD_VdqWdq(bxInstruction_c *i);
BX_SMF void PSADBW_VdqWdq(bxInstruction_c *i);
BX_SMF void MASKMOVDQU_VdqVRdq(bxInstruction_c *i);
BX_SMF void PSUBB_VdqWdq(bxInstruction_c *i);
BX_SMF void PSUBW_VdqWdq(bxInstruction_c *i);
BX_SMF void PSUBD_VdqWdq(bxInstruction_c *i);
BX_SMF void PSUBQ_PqQq(bxInstruction_c *i);
BX_SMF void PSUBQ_VdqWdq(bxInstruction_c *i);
BX_SMF void PADDB_VdqWdq(bxInstruction_c *i);
BX_SMF void PADDW_VdqWdq(bxInstruction_c *i);
BX_SMF void PADDD_VdqWdq(bxInstruction_c *i);
BX_SMF void PSRLW_PdqIb(bxInstruction_c *i);
BX_SMF void PSRAW_PdqIb(bxInstruction_c *i);
BX_SMF void PSLLW_PdqIb(bxInstruction_c *i);
BX_SMF void PSRLD_PdqIb(bxInstruction_c *i);
BX_SMF void PSRAD_PdqIb(bxInstruction_c *i);
BX_SMF void PSLLD_PdqIb(bxInstruction_c *i);
BX_SMF void PSRLQ_PdqIb(bxInstruction_c *i);
BX_SMF void PSRLDQ_WdqIb(bxInstruction_c *i);
BX_SMF void PSLLQ_PdqIb(bxInstruction_c *i);
BX_SMF void PSLLDQ_WdqIb(bxInstruction_c *i);
/* SSE2 */
BX_SMF void fpu_execute(bxInstruction_c *i);
BX_SMF void fpu_init(void);
BX_SMF void fpu_print_regs (void);
@ -2287,9 +2517,6 @@ union {
BX_SMF void JCXZ64_Jb(bxInstruction_c *);
#endif // #if BX_SUPPORT_X86_64
BX_SMF void FXSAVE(bxInstruction_c *i);
BX_SMF void FXRSTOR(bxInstruction_c *i);
// mch added
BX_SMF void INVLPG(bxInstruction_c *);
BX_SMF void wait_for_interrupt();
@ -3001,6 +3228,7 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
#define BxPrefix 0x0010 // bit 4
#define BxAnother 0x0020 // bit 5
#define BxSplitMod11b 0x0040 // bit 6
#define BxPrefixSSE 0x0080 // bit 7
#define BxRepeatable 0x0800 // bit 11 (pass through to metaInfo field)
#define BxRepeatableZF 0x1000 // bit 12 (pass through to metaInfo field)
#define BxGroupN 0x0100 // bits 8
@ -3013,21 +3241,12 @@ IMPLEMENT_EFLAG_ACCESSOR (TF, 8)
#define BxGroup7 BxGroupN
#define BxGroup8 BxGroupN
#define BxGroup9 BxGroupN
#define BxGroupA BxGroupN
#if BX_SUPPORT_FPU
#define BxAnotherFPU BxAnother
#else
#define BxAnotherFPU (0)
#endif
#if BX_SUPPORT_MMX
#define BxAnotherMMX BxAnother
#else
#define BxAnotherMMX (0)
#endif
#define BxGroup12 BxGroupN
#define BxGroup13 BxGroupN
#define BxGroup14 BxGroupN
#define BxGroup15 BxGroupN
#define BxGroup16 BxGroupN
#if BX_DEBUGGER
typedef enum _show_flags {

2265
bochs/cpu/fetchdecode.cc
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File diff suppressed because it is too large Load Diff

4168
bochs/cpu/fetchdecode64.cc
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File diff suppressed because it is too large Load Diff

4
bochs/cpu/i387.h
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@ -122,8 +122,8 @@ typedef union {
typedef struct mmx_physical_reg_t
{
BxPackedMmxRegister packed_mmx_register;
Bit16u exp; /* 4 bytes: exponent of fp register,
set to 0xFFFF by all mmx commands */
Bit16u exp; /* 4 bytes: exponent of FP register,
set to 0xffff by all MMX commands */
Bit32u aligment; /* 4 bytes: aligment */
} BxMmxRegister;

783
bochs/cpu/mmx.cc
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File diff suppressed because it is too large Load Diff

26
bochs/cpu/proc_ctrl.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.56 2002-10-08 14:43:18 ptrumpet Exp $
// $Id: proc_ctrl.cc,v 1.57 2002-10-16 17:37:34 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -47,14 +47,22 @@
void
BX_CPU_C::UndefinedOpcode(bxInstruction_c *i)
{
BX_DEBUG(("UndefinedOpcode: %02x causes exception 6",
(unsigned) i->b1()));
BX_DEBUG(("UndefinedOpcode: %02x causes exception 6", (unsigned) i->b1()));
exception(BX_UD_EXCEPTION, 0, 0);
}
void
BX_CPU_C::NOP(bxInstruction_c *i)
{
}
void BX_CPU_C::PREFETCH(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_INSTR_PREFETCH_HINT(CPU_ID, i->nnn(), i->seg(), RMAddr(i));
#else
UndefinedOpcode(i);
#endif
}
void
@ -1430,11 +1438,18 @@ BX_CPU_C::CPUID(bxInstruction_c *i)
features |= (1<<9); // APIC on chip
# endif
# if BX_SUPPORT_FPU
features |= 0x01; // has FPU
features |= 0x01; // support FPU
# endif
# if BX_SUPPORT_MMX
features |= (1<<23); // support MMX
# endif
# if BX_SUPPORT_SSE
features |= (1<<24); // support FSAVE/FXRSTOR
features |= (1<<25); // support SSE
# endif
# if BX_SUPPORT_SSE2
features |= (1<<26); // support SSE2
# endif
#else
BX_PANIC(("CPUID: not implemented for > 6"));
@ -2020,7 +2035,7 @@ BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size,
}
#endif
/*
void
BX_CPU_C::FXSAVE(bxInstruction_c *i)
{
@ -2031,3 +2046,4 @@ BX_CPU_C::FXRSTOR(bxInstruction_c *i)
{
BX_ERROR(("FXRSTOR is only a stub."));
}
*/

219
bochs/cpu/sse.cc
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@ -1,9 +1,32 @@
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2002 Stanislav Shwartsman
// Written by Stanislav Shwartsman <gate@fidonet.org.il>
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#define LOG_THIS BX_CPU_THIS_PTR
#if BX_SUPPORT_SSE
void BX_CPU_C::PrepareSseInstruction(void)
void BX_CPU_C::prepareSSE(void)
{
if(BX_CPU_THIS_PTR cr0.ts)
exception(BX_NM_EXCEPTION, 0, 0);
@ -14,11 +37,65 @@ void BX_CPU_C::PrepareSseInstruction(void)
if(! (BX_CPU_THIS_PTR cr4.get_OSXMMEXCPT()))
exception(BX_UD_EXCEPTION, 0, 0);
}
#define BX_MXCSR_REGISTER (BX_CPU_THIS_PTR mxcsr.mxcsr)
#endif
/* 0F AE Grp15 010 */
void BX_CPU_C::LDMXCSR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
read_virtual_dword(i->seg(), RMAddr(i), &BX_MXCSR_REGISTER);
if(BX_MXCSR_REGISTER & ~MXCSR_MASK)
exception(BX_GP_EXCEPTION, 0, 0);
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
/* 0F AE Grp15 011 */
void BX_CPU_C::STMXCSR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
Bit32u mxcsr = BX_MXCSR_REGISTER & MXCSR_MASK;
write_virtual_dword(i->seg(), RMAddr(i), &mxcsr);
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::FXSAVE(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_PANIC(("SSE Instruction FXSAVE still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::FXRSTOR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_PANIC(("SSE Instruction FXRSTOR still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::MOVUPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVUPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -29,7 +106,7 @@ void BX_CPU_C::MOVUPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR PrepareSseInstruction();
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVSS_VssWss still not implemented"));
#else
@ -41,6 +118,8 @@ void BX_CPU_C::MOVSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::MOVUPS_WpsVps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVUPS_WpsVps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -51,6 +130,8 @@ void BX_CPU_C::MOVUPS_WpsVps(bxInstruction_c *i)
void BX_CPU_C::MOVSS_WssVss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVSS_WssVss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -61,6 +142,8 @@ void BX_CPU_C::MOVSS_WssVss(bxInstruction_c *i)
void BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVLPS_VpsMq still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -71,6 +154,8 @@ void BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
void BX_CPU_C::MOVLPS_MqVps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVLPS_MqVps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -81,6 +166,8 @@ void BX_CPU_C::MOVLPS_MqVps(bxInstruction_c *i)
void BX_CPU_C::UNPCKLPS_VpsWq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction UNPCKLPS_VpsWq still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -91,6 +178,8 @@ void BX_CPU_C::UNPCKLPS_VpsWq(bxInstruction_c *i)
void BX_CPU_C::UNPCKHPS_VpsWq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction UNPCKHPS_VpsWq still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -101,6 +190,8 @@ void BX_CPU_C::UNPCKHPS_VpsWq(bxInstruction_c *i)
void BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVHPS_VpsMq still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -111,6 +202,8 @@ void BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)
void BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVHPS_MqVps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -121,6 +214,8 @@ void BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
void BX_CPU_C::MOVAPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVAPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -131,6 +226,8 @@ void BX_CPU_C::MOVAPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::MOVAPS_WpsVps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVAPS_WpsVps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -141,6 +238,8 @@ void BX_CPU_C::MOVAPS_WpsVps(bxInstruction_c *i)
void BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction CVTPI2PS_VpsQq still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -151,6 +250,8 @@ void BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
void BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction CVTSI2SS_VssEd still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -161,6 +262,8 @@ void BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
void BX_CPU_C::MOVNTPS_MdqVps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVNTPS_MdqVps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -171,6 +274,8 @@ void BX_CPU_C::MOVNTPS_MdqVps(bxInstruction_c *i)
void BX_CPU_C::CVTTPS2PI_PqWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction CVTTPS2PI_PqWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -181,6 +286,8 @@ void BX_CPU_C::CVTTPS2PI_PqWps(bxInstruction_c *i)
void BX_CPU_C::CVTTSS2SI_GdWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction CVTTSS2SI_GdWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -191,6 +298,8 @@ void BX_CPU_C::CVTTSS2SI_GdWss(bxInstruction_c *i)
void BX_CPU_C::CVTPS2PI_PqWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction CVTPS2PI_PqWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -201,6 +310,8 @@ void BX_CPU_C::CVTPS2PI_PqWps(bxInstruction_c *i)
void BX_CPU_C::CVTSS2SI_GdWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction CVTSS2SI_GdWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -211,6 +322,8 @@ void BX_CPU_C::CVTSS2SI_GdWss(bxInstruction_c *i)
void BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction UCOMISS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -221,6 +334,8 @@ void BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
void BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction COMISS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -231,6 +346,8 @@ void BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MOVMSKPS_GdVRps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -241,6 +358,8 @@ void BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
void BX_CPU_C::SQRTPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction SQRTPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -251,6 +370,8 @@ void BX_CPU_C::SQRTPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::SQRTSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction SQRTSS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -261,6 +382,8 @@ void BX_CPU_C::SQRTSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::RSQRTPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction RSQRTPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -271,6 +394,8 @@ void BX_CPU_C::RSQRTPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction RSQRTSS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -281,6 +406,8 @@ void BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::RCPPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction RCPPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -291,6 +418,8 @@ void BX_CPU_C::RCPPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction RCPSS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -301,6 +430,8 @@ void BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::ANDPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction ANDPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -311,6 +442,8 @@ void BX_CPU_C::ANDPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::ANDNPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction ANDNPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -321,6 +454,8 @@ void BX_CPU_C::ANDNPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::ORPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction ORPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -331,6 +466,8 @@ void BX_CPU_C::ORPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::XORPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction XORPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -341,6 +478,8 @@ void BX_CPU_C::XORPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::ADDPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction ADDPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -351,6 +490,8 @@ void BX_CPU_C::ADDPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::ADDSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction ADDSS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -361,6 +502,8 @@ void BX_CPU_C::ADDSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::MULPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MULPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -371,6 +514,8 @@ void BX_CPU_C::MULPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::MULSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MULSS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -381,6 +526,8 @@ void BX_CPU_C::MULSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::SUBPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction SUBPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -391,6 +538,8 @@ void BX_CPU_C::SUBPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::SUBSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction SUBSS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -401,6 +550,8 @@ void BX_CPU_C::SUBSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::MINPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MINPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -411,6 +562,8 @@ void BX_CPU_C::MINPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::MINSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MINSS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -421,6 +574,8 @@ void BX_CPU_C::MINSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::DIVPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction DIVPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -431,6 +586,8 @@ void BX_CPU_C::DIVPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::DIVSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction DIVSS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -441,6 +598,8 @@ void BX_CPU_C::DIVSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::MAXPS_VpsWps(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MAXPS_VpsWps still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -451,6 +610,8 @@ void BX_CPU_C::MAXPS_VpsWps(bxInstruction_c *i)
void BX_CPU_C::MAXSS_VssWss(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction MAXSS_VssWss still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -461,6 +622,8 @@ void BX_CPU_C::MAXSS_VssWss(bxInstruction_c *i)
void BX_CPU_C::PSHUFLW_VqWqIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction PSHUFLW_VqWqIb still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -471,6 +634,8 @@ void BX_CPU_C::PSHUFLW_VqWqIb(bxInstruction_c *i)
void BX_CPU_C::CMPPS_VpsWpsIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction CMPPS_VpsWpsIb still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -481,6 +646,8 @@ void BX_CPU_C::CMPPS_VpsWpsIb(bxInstruction_c *i)
void BX_CPU_C::CMPSS_VssWssIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction CMPSS_VssWssIb still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -491,6 +658,8 @@ void BX_CPU_C::CMPSS_VssWssIb(bxInstruction_c *i)
void BX_CPU_C::PINSRW_PqEdIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction PINSRW_PqEdIb still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -501,6 +670,8 @@ void BX_CPU_C::PINSRW_PqEdIb(bxInstruction_c *i)
void BX_CPU_C::PEXTRW_PqEdIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction PEXTRW_PqEdIb still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -511,6 +682,8 @@ void BX_CPU_C::PEXTRW_PqEdIb(bxInstruction_c *i)
void BX_CPU_C::SHUFPS_VpsWpsIb(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction SHUFPS_VpsWpsIb still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -521,6 +694,8 @@ void BX_CPU_C::SHUFPS_VpsWpsIb(bxInstruction_c *i)
void BX_CPU_C::PMOVMSKB_GdPRq(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_CPU_THIS_PTR prepareSSE();
BX_PANIC(("SSE Instruction PMOVMSKB_GdPRq still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
@ -547,43 +722,3 @@ void BX_CPU_C::MASKMOVQ_PqPRq(bxInstruction_c *i)
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::LDMXCSR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_PANIC(("SSE Instruction LDMXCSR still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::STMXCSR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_PANIC(("SSE Instruction STMXCSR still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::FXSAVE(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_PANIC(("SSE Instruction FXSAVE still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::FXRSTOR(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE
BX_PANIC(("SSE Instruction FXRSTOR still not implemented"));
#else
BX_INFO(("SSE instruction set not supported in current configuration"));
UndefinedOpcode(i);
#endif
}

298
bochs/cpu/sse2.cc
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File diff suppressed because it is too large Load Diff

66
bochs/cpu/xmm.h Normal file
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@ -0,0 +1,66 @@
#ifndef BX_SSE_EXTENSIONS_H
#define BX_SSE_EXTENSIONS_H
/* XMM REGISTER */
typedef Bit32u Float32;
typedef Bit64u Float64;
typedef union bx_xmm_reg_t {
Bit8s s8[16];
Bit16s s16[8];
Bit32s s32[4];
Bit64s s64[2];
Bit8u u8[16];
Bit16u u16[8];
Bit32u u32[4];
Bit64u u64[2];
Float32 f32[4];
Float64 f64[2];
} BxPackedXmmRegister;
#ifdef BX_SUPPORT_X86_64
# define BX_XMM_REGISTERS 16
#else
# define BX_XMM_REGISTERS 8
#endif
/* MXCSR REGISTER */
/* 31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16
* ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|== (reserved)
* 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0
*
* 15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0
* ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|==
* FZ| R C |PM|UM|OM|ZM|DM|IM|DZ|PE|UE|OE|ZE|DE|IE
*/
/* MXCSR REGISTER FIELDS DESCRIPTION */
/*
* IE 0 Invalid-Operation Exception 0
* DE 1 Denormalized-Operand Exception 0
* ZE 2 Zero-Divide Exception 0
* OE 3 Overflow Exception 0
* UE 4 Underflow Exception 0
* PE 5 Precision Exception 0
* DZ 6 Denormals are Zeros 0
* IM 7 Invalid-Operation Exception Mask 1
* DM 8 Denormalized-Operand Exception Mask 1
* ZM 9 Zero-Divide Exception Mask 1
* OM 10 Overflow Exception Mask 1
* UM 11 Underflow Exception Mask 1
* PM 12 Precision Exception Mask 1
* RC 13-14 Floating-Point Rounding Control 00
* FZ 15 Flush-to-Zero for Masked Underflow 0
*/
struct bx_mxcsr_t {
Bit32u mxcsr; /* define bitfields accessors later */
};
#define MXCSR_MASK 0x00FF /* reset reserved bits */
#define MXCSR_RESET 0x1F80 /* reset value of the MXCSR register */
#endif

14
bochs/instrument/example0/instrument.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.h,v 1.6 2002-09-29 16:05:13 sshwarts Exp $
// $Id: instrument.h,v 1.7 2002-10-16 17:37:34 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -33,11 +33,6 @@
// possible types passed to BX_INSTR_CACHE_CNTRL()
#define BX_INSTR_INVD 20
#define BX_INSTR_WBINVD 21
#define BX_INSTR_SFENCE 22
#define BX_INSTR_PREFETCH_T0 23
#define BX_INSTR_PREFETCH_T1 24
#define BX_INSTR_PREFETCH_T2 25
#define BX_INSTR_PREFETCH_NTA 26
#define BX_INSTR_IS_CALL 10
#define BX_INSTR_IS_RET 11
@ -45,6 +40,11 @@
#define BX_INSTR_IS_JMP 13
#define BX_INSTR_IS_INT 14
#define BX_INSTR_PREFETCH_NTA 00
#define BX_INSTR_PREFETCH_T0 01
#define BX_INSTR_PREFETCH_T1 02
#define BX_INSTR_PREFETCH_T2 03
#if BX_INSTRUMENTATION
@ -129,6 +129,7 @@ void bx_instr_mem_data(unsigned cpu, bx_address lin, unsigned size, unsigned rw)
/* TLB/CACHE control instruction executed */
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
# define BX_INSTR_TLB_CNTRL(cpu_id, what, newval)
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
# define BX_INSTR_REPEAT_ITERATION(cpu_id)
@ -195,6 +196,7 @@ void bx_instr_mem_data(unsigned cpu, bx_address lin, unsigned size, unsigned rw)
/* TLB/CACHE control instruction executed */
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
# define BX_INSTR_TLB_CNTRL(cpu_id, what, newval)
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
# define BX_INSTR_REPEAT_ITERATION(cpu_id)

14
bochs/instrument/example1/instrument.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.h,v 1.3 2002-09-29 16:50:29 sshwarts Exp $
// $Id: instrument.h,v 1.4 2002-10-16 17:37:35 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -33,11 +33,6 @@
// possible types passed to BX_INSTR_CACHE_CNTRL()
#define BX_INSTR_INVD 20
#define BX_INSTR_WBINVD 21
#define BX_INSTR_SFENCE 22
#define BX_INSTR_PREFETCH_T0 23
#define BX_INSTR_PREFETCH_T1 24
#define BX_INSTR_PREFETCH_T2 25
#define BX_INSTR_PREFETCH_NTA 26
#define BX_INSTR_IS_CALL 10
#define BX_INSTR_IS_RET 11
@ -45,6 +40,11 @@
#define BX_INSTR_IS_JMP 13
#define BX_INSTR_IS_INT 14
#define BX_INSTR_PREFETCH_NTA 00
#define BX_INSTR_PREFETCH_T0 01
#define BX_INSTR_PREFETCH_T1 02
#define BX_INSTR_PREFETCH_T2 03
#if BX_INSTRUMENTATION
@ -176,6 +176,7 @@ extern bxInstrumentation icpu[BX_SMP_PROCESSORS];
/* TLB/CACHE control instruction executed */
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
# define BX_INSTR_TLB_CNTRL(cpu_id, what, newval)
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
# define BX_INSTR_REPEAT_ITERATION(cpu_id)
@ -242,6 +243,7 @@ extern bxInstrumentation icpu[BX_SMP_PROCESSORS];
/* TLB/CACHE control instruction executed */
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
# define BX_INSTR_TLB_CNTRL(cpu_id, what, newval)
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
# define BX_INSTR_REPEAT_ITERATION(cpu_id)

3
bochs/instrument/stubs/instrument.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.cc,v 1.6 2002-09-29 16:10:27 sshwarts Exp $
// $Id: instrument.cc,v 1.7 2002-10-16 17:37:35 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -65,6 +65,7 @@ void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address e
void bx_instr_tlb_cntrl(unsigned cpu, unsigned what, Bit32u newval) {}
void bx_instr_cache_cntrl(unsigned cpu, unsigned what) {}
void bx_instr_prefetch_hint(unsigned cpu, unsigned what, unsigned seg, bx_address offset) {}
void bx_instr_repeat_iteration(unsigned cpu) {}

9
bochs/instrument/stubs/instrument.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: instrument.h,v 1.8 2002-10-08 21:30:50 sshwarts Exp $
// $Id: instrument.h,v 1.9 2002-10-16 17:37:35 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -46,6 +46,9 @@
#define BX_INSTR_PREFETCH_T2 03
#if BX_INSTRUMENTATION
class bxInstruction_c;
@ -89,6 +92,7 @@ void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address e
void bx_instr_tlb_cntrl(unsigned cpu, unsigned what, Bit32u newval);
void bx_instr_cache_cntrl(unsigned cpu, unsigned what);
void bx_instr_prefetch_hint(unsigned cpu, unsigned what, unsigned seg, bx_address offset);
void bx_instr_repeat_iteration(unsigned cpu);
@ -152,6 +156,8 @@ void bx_instr_phy_read(bx_address addr, unsigned len);
/* TLB/CACHE control instruction executed */
# define BX_INSTR_CACHE_CNTRL(cpu_id, what) bx_instr_cache_cntrl(cpu_id, what)
# define BX_INSTR_TLB_CNTRL(cpu_id, what, newval) bx_instr_tlb_cntrl(cpu_id, what, newval)
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset) \
bx_instr_prefetch_hint(cpu_id, what, seg, offset)
# define BX_INSTR_REPEAT_ITERATION(cpu_id) bx_instr_repeat_iteration(cpu_id)
@ -218,6 +224,7 @@ void bx_instr_phy_read(bx_address addr, unsigned len);
/* TLB/CACHE control instruction executed */
# define BX_INSTR_CACHE_CNTRL(cpu_id, what)
# define BX_INSTR_TLB_CNTRL(cpu_id, what, newval)
# define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
# define BX_INSTR_REPEAT_ITERATION(cpu_id)