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Fixed minor issues - compilation and not only

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This commit is contained in:
Stanislav Shwartsman 2008-02-13 17:06:44 +00:00
parent 457152334e
commit b929a2b2b8
4 changed files with 25 additions and 23 deletions
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6
bochs/cpu/crregs.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: crregs.h,v 1.7 2008-02-13 16:45:20 sshwarts Exp $
// $Id: crregs.h,v 1.8 2008-02-13 17:06:44 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007 Stanislav Shwartsman
@ -120,12 +120,12 @@ typedef struct bx_efer_t {
typedef struct xcr0_reg_t {
Bit32u val32; // 32bit value of register
#define BX_XR0_SUPPORT_BITS 0x3
#define BX_XCR0_SUPPORT_BITS 0x3
#define BX_XCR0_FPU_BIT 0
#define BX_XCR0_FPU_MASK (1<<BX_XCR0_FPU_BIT)
#define BX_XCR0_SSE_BIT 1
#define BX_XCR0_FPU_MASK (1<<BX_XCR0_SSE_BIT)
#define BX_XCR0_SSE_MASK (1<<BX_XCR0_SSE_BIT)
IMPLEMENT_CRREG_ACCESSORS(FPU, BX_XCR0_FPU_BIT);
#if BX_SUPPORT_SSE

4
bochs/cpu/sse_move.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_move.cc,v 1.78 2008-02-13 16:45:21 sshwarts Exp $
// $Id: sse_move.cc,v 1.79 2008-02-13 17:06:44 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -40,8 +40,6 @@ void BX_CPU_C::prepareSSE(void)
exception(BX_NM_EXCEPTION, 0, 0);
}
#define BX_MXCSR_REGISTER (BX_CPU_THIS_PTR mxcsr.mxcsr)
void BX_CPU_C::print_state_SSE(void)
{
BX_DEBUG(("MXCSR: 0x%08x\n", BX_MXCSR_REGISTER));

5
bochs/cpu/xmm.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: xmm.h,v 1.25 2008-02-02 21:46:54 sshwarts Exp $
// $Id: xmm.h,v 1.26 2008-02-13 17:06:44 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -206,7 +206,8 @@ struct BOCHSAPI bx_mxcsr_t
(BX_SUPPORT_MISALIGNED_SSE ? MXCSR_MISALIGNED_EXCEPTION_MASK : 0))
#if defined(NEED_CPU_REG_SHORTCUTS)
#define MXCSR (BX_CPU_THIS_PTR mxcsr)
#define MXCSR (BX_CPU_THIS_PTR mxcsr)
#define BX_MXCSR_REGISTER (BX_CPU_THIS_PTR mxcsr.mxcsr)
#endif
/* INTEGER SATURATION */

33
bochs/cpu/xsave.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: xsave.cc,v 1.2 2008-02-13 16:45:21 sshwarts Exp $
// $Id: xsave.cc,v 1.3 2008-02-13 17:06:44 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008 Stanislav Shwartsman
@ -56,7 +56,7 @@ void BX_CPU_C::XSAVE(bxInstruction_c *i)
BX_CPU_THIS_PTR prepareXSAVE();
BX_DEBUG(("XSAVE: save processor state XCR0=0x%08x", BX_CPU_THIS_PTR xcr.getRegister()));
BX_DEBUG(("XSAVE: save processor state XCR0=0x%08x", BX_CPU_THIS_PTR xcr0.getRegister()));
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -115,7 +115,7 @@ void BX_CPU_C::XSAVE(bxInstruction_c *i)
xmm.xmm32u(3) = (BX_CPU_THIS_PTR the_i387.fcs);
}
write_virtual_dqword_aligned(i->seg(), RMAddr(i), (Bit8u *) &xmm);
write_virtual_dqword(i->seg(), RMAddr(i), (Bit8u *) &xmm);
/*
* x87 FPU Instruction Operand (Data) Pointer Offset (32/64 bits)
@ -150,7 +150,7 @@ void BX_CPU_C::XSAVE(bxInstruction_c *i)
xmm.xmm64u(1) = 0;
xmm.xmm16u(4) = fp.exp;
write_virtual_dqword_aligned(i->seg(), RMAddr(i)+index*16+32, (Bit8u *) &xmm);
write_virtual_dqword(i->seg(), RMAddr(i)+index*16+32, (Bit8u *) &xmm);
}
}
@ -165,13 +165,13 @@ void BX_CPU_C::XSAVE(bxInstruction_c *i)
{
// save XMM8-XMM15 only in 64-bit mode
if (index < 8 || Is64BitMode()) {
write_virtual_dqword_aligned(i->seg(),
write_virtual_dqword(i->seg(),
RMAddr(i)+index*16+160, (Bit8u *) &(BX_CPU_THIS_PTR xmm[index]));
}
}
}
// skip header state update for now, required to know if the CPU feature is in its initial state
// skip header update for now, required to know if a CPU feature is in its initial state
#else
BX_INFO(("XSAVE: required XSAVE support, use --enable-xsave option"));
UndefinedOpcode(i);
@ -187,7 +187,7 @@ void BX_CPU_C::XRSTOR(bxInstruction_c *i)
BX_CPU_THIS_PTR prepareXSAVE();
BX_DEBUG(("XRSTOR: restore processor state XCR0=0x%08x", BX_CPU_THIS_PTR xcr.getRegister()));
BX_DEBUG(("XRSTOR: restore processor state XCR0=0x%08x", BX_CPU_THIS_PTR xcr0.getRegister()));
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -202,7 +202,7 @@ void BX_CPU_C::XRSTOR(bxInstruction_c *i)
Bit64u header2 = read_virtual_qword(i->seg(), RMAddr(i) + 520);
Bit64u header3 = read_virtual_qword(i->seg(), RMAddr(i) + 528);
if ((~BX_CPU_THIS_PTR xr0.getRegister() & header1) != 0) {
if ((~BX_CPU_THIS_PTR xcr0.getRegister() & header1) != 0) {
BX_ERROR(("XRSTOR: Broken header state"));
exception(BX_GP_EXCEPTION, 0, 0);
}
@ -221,7 +221,7 @@ void BX_CPU_C::XRSTOR(bxInstruction_c *i)
{
if (header1 & BX_XCR0_FPU_MASK) {
// load FPU state from XSAVE area
read_virtual_dqword_aligned(i->seg(), RMAddr(i), (Bit8u *) &xmm);
read_virtual_dqword(i->seg(), RMAddr(i), (Bit8u *) &xmm);
BX_CPU_THIS_PTR the_i387.cwd = xmm.xmm16u(0);
BX_CPU_THIS_PTR the_i387.swd = xmm.xmm16u(1);
@ -247,7 +247,7 @@ void BX_CPU_C::XRSTOR(bxInstruction_c *i)
Bit32u tag_byte = xmm.xmmubyte(4);
/* Restore x87 FPU DP */
read_virtual_dqword_aligned(i->seg(), RMAddr(i) + 16, (Bit8u *) &xmm);
read_virtual_dqword(i->seg(), RMAddr(i) + 16, (Bit8u *) &xmm);
#if BX_SUPPORT_X86_64
if (i->os64L()) {
@ -294,7 +294,7 @@ void BX_CPU_C::XRSTOR(bxInstruction_c *i)
{
// restore XMM8-XMM15 only in 64-bit mode
if (index < 8 || Is64BitMode()) {
read_virtual_dqword_aligned(i->seg(),
read_virtual_dqword(i->seg(),
RMAddr(i)+index*16+160, (Bit8u *) &(BX_CPU_THIS_PTR xmm[index]));
}
}
@ -303,7 +303,10 @@ void BX_CPU_C::XRSTOR(bxInstruction_c *i)
// initialize SSE with reset values
for(index=0; index < BX_XMM_REGISTERS; index++) {
// set XMM8-XMM15 only in 64-bit mode
if (index < 8 || Is64BitMode()) BX_CPU_THIS_PTR xmm[index] = 0;
if (index < 8 || Is64BitMode()) {
BX_CPU_THIS_PTR xmm[index].xmm64u(0) = 0;
BX_CPU_THIS_PTR xmm[index].xmm64u(1) = 0;
}
}
}
}
@ -330,7 +333,7 @@ void BX_CPU_C::XGETBV(bxInstruction_c *i)
}
RDX = 0;
RAX = BX_CPU_THIS_PTR xrc0.setRegister();
RAX = BX_CPU_THIS_PTR xcr0.getRegister();
#else
BX_INFO(("XGETBV: required XSAVE support, use --enable-xsave option"));
UndefinedOpcode(i);
@ -363,12 +366,12 @@ void BX_CPU_C::XSETBV(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0, 0);
}
if (EDX != 0 || (EAX & ~BX_XR0_SUPPORT_BITS) != 0 || (EAX & 1) == 0) {
if (EDX != 0 || (EAX & ~BX_XCR0_SUPPORT_BITS) != 0 || (EAX & 1) == 0) {
BX_ERROR(("XSETBV: Attempting to change reserved bits!"));
exception(BX_GP_EXCEPTION, 0, 0);
}
BX_CPU_THIS_PTR xrc0.setRegister(EAX);
BX_CPU_THIS_PTR xcr0.setRegister(EAX);
#else
BX_INFO(("XSETBV: required XSAVE support, use --enable-xsave option"));
UndefinedOpcode(i);