XXX This (the m68k FPE, not the glue code) is known to be broken for
68LC040/68040V and 68LC060 cpus. This is also the reason we don't
bother to add options FPU_EMULATE to the DRACO configuration file, as
DraCos only come in 68040V (very few) and 68060 variants.
XXX This (the m68k FPE, not the glue code) is known to be broken for
68LC040/68040V and 68LC060 cpus. This is also the reason we don't
bother to add options FPU_EMULATE to the DRACO configuration file, as
DraCos only come in 68040V (very few) and 68060 variants.
renamed AUDIO_ENCODING_SLINEAR and AUDIO_ENCODING_LINEAR reverts to the
NetBSD 1.2 sematics. A kernel with COMPAT_12 defined will accept
AUDIO_ENCODING_LINEAR and treat it as before, without COMPAT_12 it
will be rejected.
port, which is lifted from amiga port, plus some changes from me:
- Add support for the HP MMU to the 020/030 bus/address error handler
(mostly lifted wholesale from the old code).
- Rename addrerr and buserr to busaddrerr2030. The new name reflects that
these functions are specific to the 68020 and 68030, and that the same
handler function is used for both vectors.
The vector table is patched once we know our CPU type, before the MMU
is enabled. In the event that we're running on a CPU that we're not
configured for, simply invoke the PROM's "reboot request"; we have no
hope of running in the event of a config botch, since we need working
a working bus error handler for console initialization.
These new functions optimze for common-case page faults, eliminate
many run-time checks, and are sharable.
a global variable (yech, but i'm not out to save the world) which had
the same meaning and ended up being stealthily set in pretty much
the same place.
doing 'if (tag == ...) else if (tag == ...) else panic' rather than
by doing a switch. This makes life easier for people who need
the i386 bus_space_* functions to access spaces other than the normal
memory and I/O spaces, because it allows them to define an i386
bus_space_tag_t as a pointer to a function table, rather than just
an int. (They could define it as an int and cast it to a funtion
table pointer, but I think that's bad karma, and this change doesn't
hurt.)
mark all of 0 -> IOM_BEGIN as used, even though there are some regions
which are left for use by the BIOS (namely, the first 4k page and the
area after biosbasemem*1024 but before IOM_BEGIN). Drivers wishing to
manipulate these areas should map them specially, with _i386_memio_map()
rather than bus_space_map() or i386_memio_map().
disabled even if it's attached. If disabled, ENXIO on open.
(2) in the case where the code32 segment len overflows the I/O hole,
instead of giving up truncate it. (In other words, revert
change (2) in rev 1.21 which i suggested mistakenly.)
(3) map bios data space in the 0->640k range with _i386_memio_map()
rather than with bus_space_map(), so that no accounting checks
are done. The checks which are done to make sure that allocation
in this range is safe are sufficient.
(4) check the return value from _i386_memio_map(), and if it indicates
an error disconnect from the APM BIOS, print an error message,
and return without having marked the device 'enabled'.
functions (which only work on memory and i/o space) to i386_memio_*,
and make bus_space_* in bus.h be #defines which invoke them. This makes
life easier for people who need to define the all of the bus_space functions
so that they work on spaces other than memory and I/O space. Also, add
an _i386_memio_map function which is like i386_memio_map but doesn't do
the extent map checking or allocation. _i386_memio_map and i386_memio_*
are for use only by machine-dependent code.
code for this was in my private tree at one time, and I must have
forgotten to g/c the constant from trap.h). Reported by
enami tsugutomo <enami@but-b.or.jp>, PR #3845.
Re-arrange cpuattach() a bit so that more initialization is done before
dealing with the FPU. Some more work is still required to de-couple
FPU detection from the autoconfiguration attach code in SMP systems.
Correct handling for Trap #2 in SunOS executables,
now that we know it is supposed to flush the cache.
(Was thought to be "some obscure FPU operation".)
Add DDB interface to /sys/arch/mips/mips..
Rework heuristic stack traceback to work with DDB.
Add hooks to print exception log from DDB.
Add hooks from pmax console drivers: call Debugger()
after break from serial console, or 'DO' key from LK-xxx.
("filename" must be processed by parsebootfile() first).
Being here:
- remove the special "#ifdef MATTHIAS" mainloop
- make some "booting..." output match reality
- print '\n' and '\b' more controlled
the pc532/dev/ncr.c-inspired changes; in particular, wait for previous
transfer to complete before starting another, as we used to do. Retain
splbio() protection and simplified sbc_pdma_in().
identical to the previous incarnation.
- Update using m68k asm.h macros
- Move initialization towards the front of the file
- Rename mac68k_buserr_addr to m68k_fault_addr
- Reorganize trap 15 handler, similar in structure to -- though not as
complete as -- the hp300 version
- Reorganize doboot() for easier integration of external cache, and
make room for the latter (#ifdef __notyet__)
- General garbage collection of unused code/data
_buserr point to the 68020/030 buserr code _only_. This has broken access
error handling in the 060 support code.
This is repaired by jumping to _buserr60 from the 060SP, and by providing
a _buserr60 label identical to the _buserr in the unchanged m68k ports
using the 68060.
the 'a' partition. Sanity checked by thorpej.
This, incidently, may have been causing user errors in initializing
new disks, as described in (now closed) pr-2729 from Scott Reynolds,
because users typically don't try to edit their c partitions to be
"correct".
This can happen during perfectly normal operation if:
(a) We are using DMA to select a target, and
(b) we are interrupted by another target reselecting us.
Per discussion with Paul Krannenburg.
- If the partition is already open, skip the open/close step. (Sync with
other disk drivers).
- foosize()'s return value is in DEV_BSIZE units; adjust the size obtained
from the disklabel accordingly.
newly-exec()ed user-land process for the new dl*-capable crt0:
a0 stack pointer (points to onstack argc)
a1 rtld cleanup (filled in by dynamic loader)
a2 rtld object (filled in by dynamic loader)
a3 ps_strings
From Jason Thorpe (thorpej@nas.nasa.gov).
ktlbmiss on the kernel stack. It was showing the temporary SP, not the
original SP.
Add a display of the first few wired entries of the TLB so when the ktblmiss
occurs, the TLB entries mapping the kernel stack can be verified.
* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.
* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.
* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if
* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).
Add `options MIPS3' to pmax/conf/GENERIC.
Remove unused debug procedure I forgot to remove previously.
Consolidate the vm_page_free1() calls in pmap_release(). Duplicate code
was a result of the way I merged the MIPS3 support from the pica pmap.c.
Enhance the comment on flushing the cache when releasing the segmap pages,
and add a comment about the currently unused code to uncache pages in
pmap_enter_pv().
unsigned cause register wouldn't have worked.
Add missing ')' in trapdump that shows up when compiled with DEBUG.
Fix (unfix?) previous change to printf formats in mips3_dump_tlb: vad_to_pfn
is now consistant with single-CPU and merged-CPU support.
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.
* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S
* Garbage-collect MachHitFlushDCache()
* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.
now be installed on any partition.
Allow PRIM_LOADSZ to be set in the Makefile.
This together allows to make bootable 720k floppys.
closes PR port-i386/3751
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.
Use same cachesize variables for mips1 and mips3, and rename the variables
per Jonathan's request.
the stack frame when usermode interrupt occurs. The interrupt may have
modified the PC [such as sendsig()]. This got dropped with the stackframe
changes.
Remove old code now that the new version is working.
Correct typo for 16K cache (R4400).
Align the saved AT register location; seems to hang if not aligned on 8
byte boundry.
similar design and code by Jason Thorpe and Jonathan Stone.
NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.
mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.
mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.
mips/include/mips1_pte.h:
mips1 TLB bit definitions.
mips/include/mips3_pte.h:
mips3 TLB bit definitions.
mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.
mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.
mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.
mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)
mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.
mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().
pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
an 68060/68LC060, possibly switching on the 68060 FPU, instead of trusting
the value passed from the ROM OS to us by the bootblock.
Most 68060 boards, unlike the DraCo (which seems to have heavily patched OS
ROMs) don't set the AMIGA_68060 flag; instead, upon detecting an 68060, its
FPU is disabled to make the ROM scheduler work, and at a much later time (at
least, later than bootblock booting time), the "68060.library" installs the
Motorola 68060 software support, patches the scheduler for the 68060 FPU, and
re-enables the FPU.
Maybe this will be fixed one day, if Amiga International sells upgraded OS
ROMs which know about the 68060. Until then, and for legacy machines, this
kludge is needed if we want to boot a non-DraCo 68060.
Btw, thats why this is NOT in std.amiga, but in GENERIC; the DRACO
configuration doesn't need it (and I still plan to make std.draco go away).
* Finish new ARP (struct ethercom) changes.
Some references to sc_ac were left danglnig.
* Include if_dl.h and if_media.h.
* Delint printf() messages: int vs. long , int vs. pointer.
* Delete unused variables.
* add prototypes to <dma.h> for the per-device dma-setup functions.
* MachEmptyWriteBuffer() -> wbflush(). Also #include <bus.h>,
so that wbflush() expants to the locore callback vector entrypoint.
Move mips-specific pmap definitions (PMAP_PREFER for mips3, declaratin
of pmap_bootstrap() for the system-specific machdep.c) from
arch/pmax/include/pmap.h to arch/mips/include/pmap.h.
* rewrite findroot() based on NetBSD 1.2F i386 findoot().
* Rewrite makebootdev() to use struct devnametodevmaj pica_nam2blk[].
Previous changes changed the `devname' char array and findroot()
bot not makebootdev().
* Add prototypes, delint for gcc -Wall.
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.
* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
Change pmax/include/psl.h to just do #include <mips/psl.h>.
pmax/include/psl.h would go away completely if it wasn't stil required
by compat/common/kern_exit_43.c.
Simplify the way transmit buffers are managed, remove assumptions about
NBPG, simplify sonic_get handling, update snioctl to be more like other
current drivers, and probably a few other changes I've now forgotten about.
or swap partitions. Booting from a miniroot on the swap partition will
detect the miniroot as the boot partition (if the bootblock loader passes
the boot partition offset to the kernel).
processing from generic trap processing, _FORKBRAINDAMAGE is gone -
user process entered through proc_trampoline(), mini-debugger from pica
port.
More merged MIPS1/MIPS3 support for DECstations.
proc_trampoline(); move away from UADDR access to user structure.
From Toru Nishimura: exception trapframe changes, mini-debugger from pica
port, separate out syscall exception.
DECstation MIPS3 support: wbflush() is cpu-dependent, MIPS3 level 2 cache
support.
jtk