More merged MIPS1/MIPS3 support for DECstations.
From Toru Nishimura: separate out FP registers in user pcb.
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mhitch
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4eb69e0839
commit
bbd8bca4a4
@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.78 1997/06/12 15:46:42 mrg Exp $ */
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/* $NetBSD: machdep.c,v 1.79 1997/06/15 18:18:57 mhitch Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -226,7 +226,6 @@ extern void
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mach_init __P((int argc, char *argv[], u_int code,
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const struct callback *cv));
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#ifdef DS5000_200
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void kn02_enable_intr __P ((u_int slotno,
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int (*handler) __P((intr_arg_t sc)),
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@ -264,7 +263,6 @@ void prom_halt __P((int, char *)) __attribute__((__noreturn__));
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extern void stacktrace __P((void)); /*XXX*/
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#endif
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/*
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* safepri is a safe priority for sleep to set for a spin-wait
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* during autoconfiguration or after a panic.
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@ -272,8 +270,7 @@ extern void stacktrace __P((void)); /*XXX*/
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int safepri = PSL_LOWIPL;
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struct user *proc0paddr;
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struct proc nullproc; /* for use by swtch_exit() */
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struct proc nullproc; /* for use by switch_exit() */
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/*
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* XXX locore callback-vector setup should be done via mips_vector_init()
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@ -281,7 +278,12 @@ struct proc nullproc; /* for use by swtch_exit() */
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* explicitly call the mips1 setup function.
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*/
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extern void mips1_vector_init __P((void));
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extern void mips3_vector_init __P((void));
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extern void mips3_SetWIRED __P((int));
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extern void MachHitFlushDCache __P((vm_offset_t, int));
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extern void savefpregs __P((struct proc *));
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/*
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* Do all the stuff that locore normally does before calling main().
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@ -324,12 +326,31 @@ mach_init(argc, argv, code, cv)
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* Initialize locore-function vector.
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* Clear out the I and D caches.
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*/
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#ifdef notyet
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/* XXX locore doesn't set up cpu type early enough for this */
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mips_vector_init();
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#else
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mips1_vector_init();
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switch (cpu_id.cpu.cp_imp) {
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#ifdef MIPS1
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case MIPS_R2000:
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case MIPS_R3000:
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cpu_arch = 1;
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mips1_TLBFlush();
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for (i = 0; i < VMMACH_MIPS_3K_FIRST_RAND_ENTRY; ++i)
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mips1_TLBWriteIndexed(i, MACH_CACHED_MEMORY_ADDR, 0);
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mips1_vector_init();
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break;
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#endif
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#ifdef MIPS3
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case MIPS_R4000:
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cpu_arch = 3;
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mips3_SetWIRED(0);
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mips3_TLBFlush();
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mips3_SetWIRED(VMMACH_WIRED_ENTRIES);
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mips3_vector_init();
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break;
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#endif
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default:
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printf("CPU type (%d) not supported\n", cpu_id.cpu.cp_imp);
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prom_halt(RB_HALT, NULL);
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}
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/* look at argv[0] and compute bootdev */
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makebootdev(argv[0]);
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@ -383,34 +404,62 @@ mach_init(argc, argv, code, cv)
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* Init mapping for u page(s) for proc[0], pm_tlbpid 1.
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*/
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start = v;
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curproc->p_addr = proc0paddr = (struct user *)v;
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curproc->p_md.md_regs = proc0paddr->u_pcb.pcb_regs;
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proc0.p_addr = proc0paddr = (struct user *)v;
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curpcb = (struct pcb *)proc0.p_addr;
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proc0.p_md.md_regs = proc0paddr->u_pcb.pcb_regs;
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firstaddr = MACH_CACHED_TO_PHYS(v);
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#ifdef MIPS3
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for (i = 0; i < UPAGES; i+=2) {
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struct tlb tlb;
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tlb.tlb_mask = PG_SIZE_4K;
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tlb.tlb_hi = vad_to_vpn((UADDR + (i << PGSHIFT))) | 1;
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tlb.tlb_lo0 = vad_to_pfn(firstaddr) | PG_V | PG_M | PG_CACHED;
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tlb.tlb_lo1 = vad_to_pfn(firstaddr + NBPG) | PG_V | PG_M | PG_CACHED;
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proc0.p_md.md_upte[i] = tlb.tlb_lo0;
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proc0.p_md.md_upte[i+1] = tlb.tlb_lo1;
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mips3_TLBWriteIndexedVPS(i,&tlb);
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firstaddr += NBPG * 2;
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}
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#else
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for (i = 0; i < UPAGES; i++) {
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MachTLBWriteIndexed(i,
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mips1_TLBWriteIndexed(i,
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(UADDR + (i << PGSHIFT)) | (1 << VMMACH_TLB_PID_SHIFT),
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curproc->p_md.md_upte[i] = firstaddr | PG_V | PG_M);
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proc0.p_md.md_upte[i] = firstaddr | PG_V | PG_M);
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firstaddr += NBPG;
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}
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#endif
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v += UPAGES * NBPG;
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MachSetPID(1);
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/*
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* init nullproc for swtch_exit().
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* init nullproc for switch_exit().
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* init mapping for u page(s), pm_tlbpid 0
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* This could be used for an idle process.
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*/
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nullproc.p_addr = (struct user *)v;
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nullproc.p_md.md_regs = nullproc.p_addr->u_pcb.pcb_regs;
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bcopy("nullproc", nullproc.p_comm, sizeof("nullproc"));
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#ifdef MIPS3
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for (i = 0; i < UPAGES; i+=2) {
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nullproc.p_md.md_upte[i] = vad_to_pfn(firstaddr) | PG_V | PG_M | PG_CACHED;
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nullproc.p_md.md_upte[i+1] = vad_to_pfn(firstaddr + NBPG) | PG_V | PG_M | PG_CACHED;
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firstaddr += NBPG * 2;
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}
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#else
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for (i = 0; i < UPAGES; i++) {
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nullproc.p_md.md_upte[i] = firstaddr | PG_V | PG_M;
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firstaddr += NBPG;
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}
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#endif
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v += UPAGES * NBPG;
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/* clear pages for u areas */
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bzero(start, v - start);
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#ifdef MIPS3
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mips3_FlushDCache(MACH_CACHED_TO_PHYS(start), v - start);
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MachHitFlushDCache(UADDR, UPAGES * NBPG);
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#endif
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/*
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* Determine what model of computer we are running on.
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@ -428,7 +477,8 @@ mach_init(argc, argv, code, cv)
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}
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}
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/* check for MIPS based platform */
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if (((i >> 24) & 0xFF) != 0x82) {
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/* 0x82 -> MIPS1, 0x84 -> MIPS3 */
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if (((i >> 24) & 0xFF) != 0x82 && ((i >> 24) & 0xff) != 0x84) {
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printf("Unknown System type '%s' 0x%x\n", cp, i);
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cpu_reboot(RB_HALT | RB_NOSYNC, NULL);
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}
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@ -616,7 +666,11 @@ mach_init(argc, argv, code, cv)
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Mach_reset_addr =
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(u_int*)MACH_PHYS_TO_UNCACHED(XINE_REG_TIMEOUT);
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(*Mach_reset_addr) = 0;
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#ifdef MIPS3
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strcpy(cpu_model, "5000/50"); /* XXX */
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#else
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strcpy(cpu_model, "5000/25");
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#endif
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break;
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#endif /*DS5000_25*/
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@ -664,7 +718,11 @@ mach_init(argc, argv, code, cv)
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/* clear any memory errors from probes */
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*Mach_reset_addr = 0;
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#ifdef MIPS3
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strcpy(cpu_model, "5000/260"); /*XXX*/
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#else
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strcpy(cpu_model, "5000/240");
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#endif
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break;
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#endif /* DS5000_240 */
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@ -804,8 +862,6 @@ mach_init(argc, argv, code, cv)
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pmap_bootstrap((vm_offset_t)v);
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}
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/*
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* cpu_startup: allocate memory for variable-sized tables,
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* initialize cpu, and do autoconfiguration.
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@ -952,16 +1008,17 @@ setregs(p, pack, stack, retval)
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u_long stack;
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register_t *retval;
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{
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extern struct proc *machFPCurProcPtr;
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extern struct proc *fpcurproc;
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bzero((caddr_t)p->p_md.md_regs, (FSR + 1) * sizeof(int));
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bzero((caddr_t)p->p_md.md_regs, sizeof(struct frame));
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bzero((caddr_t)&p->p_addr->u_pcb.pcb_fpregs, sizeof(struct fpreg));
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p->p_md.md_regs[SP] = stack;
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p->p_md.md_regs[PC] = pack->ep_entry & ~3;
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p->p_md.md_regs[T9] = pack->ep_entry & ~3; /* abicall requirement */
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p->p_md.md_regs[PS] = PSL_USERSET;
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p->p_md.md_flags &= ~MDP_FPUSED;
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if (machFPCurProcPtr == p)
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machFPCurProcPtr = (struct proc *)0;
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if (fpcurproc == p)
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fpcurproc = (struct proc *)0;
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}
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/*
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@ -1033,20 +1090,19 @@ sendsig(catcher, sig, mask, code)
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ksc.sc_onstack = oonstack;
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ksc.sc_mask = mask;
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ksc.sc_pc = regs[PC];
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ksc.mullo = regs [MULLO];
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ksc.mulhi = regs [MULHI];
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ksc.mullo = regs[MULLO];
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ksc.mulhi = regs[MULHI];
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ksc.sc_regs[ZERO] = 0xACEDBADE; /* magic number */
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bcopy((caddr_t)®s[1], (caddr_t)&ksc.sc_regs[1],
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sizeof(ksc.sc_regs) - sizeof(int));
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sizeof(ksc.sc_regs) - sizeof(ksc.sc_regs[0]));
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ksc.sc_fpused = p->p_md.md_flags & MDP_FPUSED;
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if (ksc.sc_fpused) {
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extern struct proc *machFPCurProcPtr;
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extern struct proc *fpcurproc;
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/* if FPU has current state, save it first */
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if (p == machFPCurProcPtr)
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MachSaveCurFPState(p);
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bcopy((caddr_t)&p->p_md.md_regs[F0], (caddr_t)ksc.sc_fpregs,
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sizeof(ksc.sc_fpregs));
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if (p == fpcurproc)
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savefpregs(p);
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*(struct fpreg *)ksc.sc_fpregs = p->p_addr->u_pcb.pcb_fpregs;
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}
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if (copyout((caddr_t)&ksc, (caddr_t)&fp->sf_sc, sizeof(ksc))) {
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/*
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@ -1145,10 +1201,9 @@ sys_sigreturn(p, v, retval)
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regs[MULLO] = scp->mullo;
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regs[MULHI] = scp->mulhi;
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bcopy((caddr_t)&scp->sc_regs[1], (caddr_t)®s[1],
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sizeof(scp->sc_regs) - sizeof(int));
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sizeof(scp->sc_regs) - sizeof(scp->sc_regs[0]));
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if (scp->sc_fpused)
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bcopy((caddr_t)scp->sc_fpregs, (caddr_t)&p->p_md.md_regs[F0],
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sizeof(scp->sc_fpregs));
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p->p_addr->u_pcb.pcb_fpregs = *(struct fpreg *)scp->sc_fpregs;
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return (EJUSTRETURN);
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}
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@ -1283,7 +1338,7 @@ cpu_reboot(howto, bootstr)
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/* take a snap shot before clobbering any registers */
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if (curproc)
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savectx(curproc->p_addr);
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savectx((struct user *)curpcb);
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#ifdef DEBUG
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if (panicstr)
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