Pull in latest Amiga bus/address error handling.
This commit is contained in:
leo
parent
15de91e26d
commit
a323500b0f
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@ -1,4 +1,4 @@
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/* $NetBSD: atari_init.c,v 1.31 1997/06/10 18:37:50 veego Exp $ */
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/* $NetBSD: atari_init.c,v 1.32 1997/07/05 20:50:41 leo Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman
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@ -143,6 +143,7 @@ u_long st_pool_virt, st_pool_phys;
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* Some of the code in here is `stolen' from Amiga MACH, and was
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* written by Bryan Ford and Niklas Hallqvist.
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*
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* Very crude 68040 support by Michael L. Hitch.
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*/
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void
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@ -208,17 +209,17 @@ char *esym_addr; /* Address of kernel '_esym' symbol */
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PAGE_MASK = NBPG-1;
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PAGE_SHIFT = PG_SHIFT;
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/*
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* Initialize cpu specific stuff
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*/
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initcpu();
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/*
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* Determine the type of machine we are running on. This needs
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* to be done early!
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*/
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set_machtype();
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/*
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* Initialize cpu specific stuff
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*/
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initcpu();
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/*
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* We run the kernel from ST memory at the moment.
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* The kernel segment table is put just behind the loaded image.
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@ -906,48 +907,70 @@ int m68060_pcr_init = 0x21; /* make this patchable */
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static void
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initcpu()
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{
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/* XXX should init '40 vecs here, too */
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typedef void trapfun __P((void));
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switch (cputype) {
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#if defined(M68060)
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extern caddr_t vectab[256];
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case CPU_68060:
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{
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extern trapfun *vectab[256];
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extern trapfun buserr60, addrerr4060, fpfault;
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#if defined(M060SP)
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extern u_int8_t FP_CALL_TOP[], I_CALL_TOP[];
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#else
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extern trapfun illinst;
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#endif
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asm volatile ("movl %0,d0; .word 0x4e7b,0x0808" : :
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"d"(m68060_pcr_init):"d0" );
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/* bus/addrerr vectors */
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vectab[2] = buserr60;
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vectab[3] = addrerr4060;
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#if defined(M060SP)
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extern u_int8_t FP_CALL_TOP[], I_CALL_TOP[];
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/* integer support */
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vectab[61] = (trapfun *)&I_CALL_TOP[128 + 0x00];
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/* floating point support */
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/*
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* XXX maybe we really should run-time check for the
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* stack frame format here:
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*/
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vectab[11] = (trapfun *)&FP_CALL_TOP[128 + 0x30];
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vectab[55] = (trapfun *)&FP_CALL_TOP[128 + 0x38];
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vectab[60] = (trapfun *)&FP_CALL_TOP[128 + 0x40];
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vectab[54] = (trapfun *)&FP_CALL_TOP[128 + 0x00];
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vectab[52] = (trapfun *)&FP_CALL_TOP[128 + 0x08];
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vectab[53] = (trapfun *)&FP_CALL_TOP[128 + 0x10];
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vectab[51] = (trapfun *)&FP_CALL_TOP[128 + 0x18];
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vectab[50] = (trapfun *)&FP_CALL_TOP[128 + 0x20];
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vectab[49] = (trapfun *)&FP_CALL_TOP[128 + 0x28];
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#else
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extern u_int8_t illinst;
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vectab[61] = illinst;
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#endif
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extern u_int8_t fpfault;
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vectab[48] = fpfault;
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}
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break;
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#endif /* defined(M68060) */
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#if defined(M68040)
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case CPU_68040:
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{
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extern trapfun *vectab[256];
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extern trapfun buserr40, addrerr4060;
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if (cputype == CPU_68060) {
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asm volatile ("movl %0,d0; .word 0x4e7b,0x0808" : :
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"d"(m68060_pcr_init):"d0" );
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#if defined(M060SP)
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/* integer support */
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vectab[61] = &I_CALL_TOP[128 + 0x00];
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/* floating point support */
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/*
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* XXX maybe we really should run-time check for the
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* stack frame format here:
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*/
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vectab[11] = &FP_CALL_TOP[128 + 0x30];
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vectab[55] = &FP_CALL_TOP[128 + 0x38];
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vectab[60] = &FP_CALL_TOP[128 + 0x40];
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vectab[54] = &FP_CALL_TOP[128 + 0x00];
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vectab[52] = &FP_CALL_TOP[128 + 0x08];
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vectab[53] = &FP_CALL_TOP[128 + 0x10];
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vectab[51] = &FP_CALL_TOP[128 + 0x18];
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vectab[50] = &FP_CALL_TOP[128 + 0x20];
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vectab[49] = &FP_CALL_TOP[128 + 0x28];
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#else
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vectab[61] = &illinst;
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#endif
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vectab[48] = &fpfault;
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/* bus/addrerr vectors */
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vectab[2] = buserr40;
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vectab[3] = addrerr4060;
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}
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break;
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#endif /* defined(M68040) */
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}
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DCIS();
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#endif
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}
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#ifdef DEBUG
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.s,v 1.43 1997/07/04 20:52:50 is Exp $ */
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/* $NetBSD: locore.s,v 1.44 1997/07/05 20:51:14 leo Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -86,32 +86,28 @@ _doadump:
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#include <m68k/m68k/trap_subr.s>
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.globl _trap, _nofault, _longjmp
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.globl _buserr60 | for 060SP
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#if defined(M68040) || defined(M68060)
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.globl _addrerr4060
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_addrerr4060:
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clrl sp@- | stack adjust count
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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movl sp@(FR_HW+8),sp@-
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clrl sp@- | dummy code
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movl #T_ADDRERR,sp@- | mark address error
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jra _ASM_LABEL(faultstkadj) | and deal with it
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#endif /* defined(M68040) || defined(M68060) */
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#if defined(M68060)
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.globl _buserr60
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_buserr60:
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_buserr:
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tstl _nofault | device probe?
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jeq _addrerr | no, handle as usual
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movl _nofault,sp@- | yes,
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jbsr _longjmp | longjmp(nofault)
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_addrerr:
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clrl sp@- | stack adjust count
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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lea sp@(FR_HW),a1 | grab base of HW berr frame
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cmpl #MMU_68040,_mmutype
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jne Lbe030
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movl a1@(8),sp@- | V = exception address
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clrl sp@- | dummy code
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moveq #0,d0
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movw a1@(6),d0 | get vector offset
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andw #0x0fff,d0
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cmpw #12,d0 | is it address error
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jeq Lisaerr
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#ifdef M68060
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cmpl #CPU_68060,_cputype | is it 68060?
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jne Lbe040
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movel a1@(12),d0 | FSLW
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clrl sp@- | stack adjust count
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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movel sp@(FR_HW+12),d0 | FSLW
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btst #2,d0 | branch prediction error?
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jeq Lnobpe
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movc cacr,d2
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@ -120,116 +116,145 @@ _addrerr:
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movl d0,d1
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addql #1,L60bpe
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andl #0x7ffd,d1
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jeq _ASM_LABEL(faultstkadjnotrap)
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jeq _ASM_LABEL(faultstkadjnotrap2)
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Lnobpe:
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movl d0,sp@ | code is FSLW now.
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| we need to adjust for misaligned addresses
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movl a1@(8),d1 | grab VA
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movl sp@(FR_HW+8),d1 | grab VA
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btst #27,d0 | check for mis-aligned access
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jeq Lberr3 | no, skip
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addl #28,d1 | yes, get into next page
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| operand case: 3,
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| instruction case: 4+12+12
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| XXX instr. case not done yet
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andl #PG_FRAME,d1 | and truncate
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Lberr3:
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movl d1,sp@(4)
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movl d1,sp@-
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movl d0,sp@- | code is FSLW now.
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andw #0x1f80,d0
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jeq Lisberr
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jra Lismerr
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Lbe040:
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#endif /* M68060 */
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movl a1@(20),d1 | get fault address
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movl #T_MMUFLT,sp@- | show that we are an MMU fault
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jra _ASM_LABEL(faultstkadj) | and deal with it
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#endif /* defined(M68060) */
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#if defined(M68040)
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.globl _buserr40
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_buserr40:
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clrl sp@- | stack adjust count
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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movl sp@(FR_HW+20),d1 | get fault address
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moveq #0,d0
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movw a1@(12),d0 | get SSW
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btst #11,d0 | check for mis-aligned
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jeq Lbe1stpg | no skip
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addl #3,d1 | get into next page
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andl #PG_FRAME,d1 | and truncate
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movw sp@(FR_HW+12),d0 | get SSW
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btst #11,d0 | check for mis-aligned
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jeq Lbe1stpg | no skip
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addl #3,d1 | get into next page
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andl #PG_FRAME,d1 | and truncate
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Lbe1stpg:
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movl d1,sp@(4) | pass fault address.
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movl d0,sp@ | pass SSW as code
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btst #10,d0 | test ATC
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jeq Lisberr | it's a bus error
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jra Lismerr
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Lbe030:
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movl d1,sp@- | pass fault address.
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movl d0,sp@- | pass SSW as code
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btst #10,d0 | test ATC
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jeq Lisberr | it is a bus error
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movl #T_MMUFLT,sp@- | show that we are an MMU fault
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jra _ASM_LABEL(faultstkadj) | and deal with it
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#endif /* defined(M68040) */
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/*
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* This is where the default vectors end-up!
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*/
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_buserr:
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_addrerr:
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#if !(defined(M68020) || defined(M68030))
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jra _badtrap
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#else
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clrl sp@- | stack adjust count
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moveml #0xFFFF,sp@- | save user registers
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movl usp,a0 | save the user SP
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movl a0,sp@(FR_SP) | in the savearea
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moveq #0,d0
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movw a1@(10),d0 | grab SSW for fault processing
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btst #12,d0 | RB set?
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jeq LbeX0 | no, test RC
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bset #14,d0 | yes, must set FB
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movw d0,a1@(10) | for hardware too
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movw sp@(FR_HW+10),d0 | grab SSW for fault processing
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btst #12,d0 | RB set?
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jeq LbeX0 | no, test RC
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bset #14,d0 | yes, must set FB
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movw d0,sp@(FR_HW+10) | for hardware too
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LbeX0:
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btst #13,d0 | RC set?
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jeq LbeX1 | no, skip
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bset #15,d0 | yes, must set FC
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movw d0,a1@(10) | for hardware too
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btst #13,d0 | RC set?
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jeq LbeX1 | no, skip
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bset #15,d0 | yes, must set FC
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movw d0,sp@(FR_HW+10) | for hardware too
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LbeX1:
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btst #8,d0 | data fault?
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jeq Lbe0 | no, check for hard cases
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movl a1@(16),d1 | fault address is as given in frame
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jra Lbe10 | thats it
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btst #8,d0 | data fault?
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jeq Lbe0 | no, check for hard cases
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movl sp@(FR_HW+16),d1 | fault address is as given in frame
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jra Lbe10 | thats it
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Lbe0:
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btst #4,a1@(6) | long (type B) stack frame?
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jne Lbe4 | yes, go handle
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movl a1@(2),d1 | no, can use save PC
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btst #14,d0 | FB set?
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jeq Lbe3 | no, try FC
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addql #4,d1 | yes, adjust address
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jra Lbe10 | done
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btst #4,sp@(FR_HW+6) | long (type B) stack frame?
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jne Lbe4 | yes, go handle
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movl sp@(FR_HW+2),d1 | no, can use save PC
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btst #14,d0 | FB set?
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jeq Lbe3 | no, try FC
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addql #4,d1 | yes, adjust address
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jra Lbe10 | done
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Lbe3:
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btst #15,d0 | FC set?
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jeq Lbe10 | no, done
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addql #2,d1 | yes, adjust address
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jra Lbe10 | done
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btst #15,d0 | FC set?
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jeq Lbe10 | no, done
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addql #2,d1 | yes, adjust address
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jra Lbe10 | done
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Lbe4:
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movl a1@(36),d1 | long format, use stage B address
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btst #15,d0 | FC set?
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jeq Lbe10 | no, all done
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subql #2,d1 | yes, adjust address
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movl sp@(FR_HW+36),d1 | long format, use stage B address
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btst #15,d0 | FC set?
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jeq Lbe10 | no, all done
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subql #2,d1 | yes, adjust address
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Lbe10:
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movl d1,sp@- | push fault VA
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movl d0,sp@- | and padded SSW
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movw a1@(6),d0 | get frame format/vector offset
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andw #0x0FFF,d0 | clear out frame format
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cmpw #12,d0 | address error vector?
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jeq Lisaerr | yes, go to it
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movl d1,a0 | fault address
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movl sp@,d0 | function code from ssw
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btst #8,d0 | data fault?
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movl d1,sp@- | push fault VA
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movl d0,sp@- | and padded SSW
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movw sp@(FR_HW+8+6),d0 | get frame format/vector offset
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andw #0x0FFF,d0 | clear out frame format
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cmpw #12,d0 | address error vector?
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jeq Lisaerr | yes, go to it
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movl d1,a0 | fault address
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movl sp@,d0 | function code from ssw
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btst #8,d0 | data fault?
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jne Lbe10a
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movql #1,d0 | user program access FC
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| (we don't separate data/program)
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btst #5,a1@ | supervisor mode?
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jeq Lbe10a | if no, done
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movql #5,d0 | else supervisor program access
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movql #1,d0 | user program access FC
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| (we dont seperate data/program)
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btst #5,sp@(FR_HW+8) | supervisor mode?
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jeq Lbe10a | if no, done
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movql #5,d0 | else supervisor program access
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Lbe10a:
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ptestr d0,a0@,#7 | do a table search
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pmove psr,sp@ | save result
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ptestr d0,a0@,#7 | do a table search
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pmove psr,sp@ | save result
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movb sp@,d1
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btst #2,d1 | invalid (incl. limit viol. and berr)?
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jeq Lmightnotbemerr | no -> wp check
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btst #7,d1 | is it a MMU table berr?
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jeq Lismerr | no, must be fast
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jra Lisberr1 | real bus err needs not be fast
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btst #2,d1 | invalid (incl. limit viol. and berr)?
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jeq Lmightnotbemerr | no -> wp check
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btst #7,d1 | is it MMU table berr?
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jeq Lismerr | no, must be fast
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jra Lisberr1 | real bus err needs not be fast.
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Lmightnotbemerr:
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btst #3,d1 | write protect bit set?
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jeq Lisberr1 | no: must be bus error
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movl sp@,d0 | ssw into low word of d0
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andw #0xc0,d0 | Write protect is set on page:
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cmpw #0x40,d0 | was it a read cycle?
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jeq Lisberr1 | yes, was not WPE, must be bus error
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btst #3,d1 | write protect bit set?
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jeq Lisberr1 | no: must be bus error
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movl sp@,d0 | ssw into low word of d0
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andw #0xc0,d0 | Write protect is set on page:
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cmpw #0x40,d0 | was it read cycle?
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jeq Lisberr1 | yes, was not WPE, must be bus err
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Lismerr:
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movl #T_MMUFLT,sp@- | show that we are an MMU fault
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jra _ASM_LABEL(faultstkadj) | and deal with it
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movl #T_MMUFLT,sp@- | show that we are an MMU fault
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jra _ASM_LABEL(faultstkadj) | and deal with it
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Lisaerr:
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movl #T_ADDRERR,sp@- | mark address error
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jra _ASM_LABEL(faultstkadj) | and deal with it
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movl #T_ADDRERR,sp@- | mark address error
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jra _ASM_LABEL(faultstkadj) | and deal with it
|
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Lisberr1:
|
||||
clrw sp@ | re-clear pad word
|
||||
Lisberr:
|
||||
movl #T_BUSERR,sp@- | mark bus error
|
||||
jra _ASM_LABEL(faultstkadj) | and deal with it
|
||||
clrw sp@ | re-clear pad word
|
||||
#endif /* !(defined(M68020) || defined(M68030)) */
|
||||
|
||||
Lisberr: | also used by M68040/60
|
||||
tstl _nofault | device probe?
|
||||
jeq LberrIsProbe | no, handle as usual
|
||||
movl _nofault,sp@- | yes,
|
||||
jbsr _longjmp | longjmp(nofault)
|
||||
/* NOTREACHED */
|
||||
LberrIsProbe:
|
||||
movl #T_BUSERR,sp@- | mark bus error
|
||||
jra _ASM_LABEL(faultstkadj) | and deal with it
|
||||
|
||||
/*
|
||||
* FP exceptions.
|
||||
|
|
|
|||
Loading…
Reference in New Issue