the Completion Timeout Prefix/Header Log Capable bit in the AER capability
and control register (ECN: Downstream Port Containment (DPC)).
- Add the Poisoned TLP Egress Block bit (ECN: Enhanced DPC).
- Update Link Capabilities 2 register and Link Control 3 register (ECN:
Separate Refclk Independent SSC Architecture (SRIS))
- ECN: Readiness Notifications (RN)
- Add the Retimer Presence Detect Supported bit in the Link Capabilities 2
register and the Retimer Presence Detected bit in the Link Status 2 register
(ECN: Extension Devices)
- Add the Structure Length field in AF capability register.
- Add Enhanced Allocation extended capability ID (ECN: Enhanced Allocation (EA)
for Memory and I/O Resources).
- Add LN System CLS (ECN: Lightweight Notification (LN) Protocol).
- Add ST Upper and Lower bit definitions (ECN: TLP Processiong Hints).
- Add the Global Invalidate bit in the ATS capability register and the PRG
Response PASID Required bit in the Page Request status register (ECN: PASID
Translation)
- Decode ASPM support bit more (ECN: ASPM Optionally)
- Use __BITS()
As wrote in the comment, HyperTransport capability appears multiple times.
pci_conf_cap() reruns only the first entry, so it can't be used here.
- Try to decode HyperTransport capability. Currently, the capability type
of each HyperTransport capability is printed and only the MSI Mapping
capability is decoded.
- Style change.
- In PCI-X cap, print 2nd bus's PCI-X mode, error protection type, Max clock
frequency and Max clock period.
- In SATA cap, print register location correctly.
- In Virtual Channel cap, print reference clock with "ns".
- In Root Complex Link Declaration, print Link Entry number.
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific
is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
the capability list part but in the detail part.
it.
- Print the cache line size in bytes.
- Print the Link Status 2 register itself.
- Some bits were not printed if the bit is 0. Always print them using with
onoff() macro.
- Print more bits.
- KNF.
- Use macro.
- Add comments.
- Print Link related registers only if the device is PCI Express Endpoint,
Legacy PCI Express Endpoint or Root Port of PCI Express Root Complex.
- Don't print Root related registers if the device is Root Complex
Integrated Endpoint and print if the device is Root Complex Event Collector.
- Not Gb/s but GT/s.
For example, 82801I PCI Express Port #1 (devid 0x2940) is really
Root Port and it has the Root Control Register and the default
value is 0 (the document say so and really 0 (Tested with my
machine)).
