No functional change:
- Add comments. - Remove obsolete comment. - Move definitions to better location. - Rename bit definition. - KNF. - Indent.
This commit is contained in:
msaitoh
parent
098138c412
commit
9931e08a9f
@ -1,4 +1,4 @@
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/* $NetBSD: msipic.c,v 1.7 2015/08/13 04:52:40 msaitoh Exp $ */
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/* $NetBSD: msipic.c,v 1.8 2015/11/17 17:51:42 msaitoh Exp $ */
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/*
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* Copyright (c) 2015 Internet Initiative Japan Inc.
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@ -27,7 +27,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.7 2015/08/13 04:52:40 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.8 2015/11/17 17:51:42 msaitoh Exp $");
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#include "opt_intrdebug.h"
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@ -493,9 +493,9 @@ msix_set_vecctl_mask(struct pic *pic, int msix_vec, int flag)
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vecctl = bus_space_read_4(bstag, bshandle,
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entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL);
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if (flag == MSIX_VECCTL_HWMASK)
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vecctl |= PCI_MSIX_VECTCTL_HWMASK_MASK;
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vecctl |= PCI_MSIX_VECTCTL_MASK;
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else
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vecctl &= ~PCI_MSIX_VECTCTL_HWMASK_MASK;
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vecctl &= ~PCI_MSIX_VECTCTL_MASK;
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bus_space_write_4(bstag, bshandle,
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entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, vecctl);
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.143 2015/11/16 09:10:58 msaitoh Exp $ */
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/* $NetBSD: pci_subr.c,v 1.144 2015/11/17 17:51:42 msaitoh Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.143 2015/11/16 09:10:58 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.144 2015/11/17 17:51:42 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_pci.h"
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@ -3191,7 +3191,7 @@ static struct {
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pci_conf_print_page_req_cap },
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{ PCI_EXTCAP_AMD, "Reserved for AMD",
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NULL },
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{ PCI_EXTCAP_RESIZE_BAR,"Resizable BAR",
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{ PCI_EXTCAP_RESIZ_BAR, "Resizable BAR",
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NULL },
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{ PCI_EXTCAP_DPA, "Dynamic Power Allocation",
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NULL },
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@ -1,4 +1,4 @@
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/* $NetBSD: pcireg.h,v 1.109 2015/11/16 09:10:58 msaitoh Exp $ */
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/* $NetBSD: pcireg.h,v 1.110 2015/11/17 17:51:42 msaitoh Exp $ */
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/*
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* Copyright (c) 1995, 1996, 1999, 2000
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@ -36,8 +36,6 @@
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/*
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* Standardized PCI configuration information
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*
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* XXX This is not complete.
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*/
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/*
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@ -524,8 +522,6 @@ typedef u_int8_t pci_revision_t;
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#define PCI_CAP_RESERVED0 0x00
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#define PCI_CAP_PWRMGMT 0x01
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#define PCI_CAP_AGP 0x02
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#define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf)
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#define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf)
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#define PCI_CAP_VPD 0x03
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#define PCI_CAP_SLOTID 0x04
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#define PCI_CAP_MSI 0x05
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@ -535,7 +531,7 @@ typedef u_int8_t pci_revision_t;
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#define PCI_CAP_VENDSPEC 0x09
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#define PCI_CAP_DEBUGPORT 0x0a
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#define PCI_CAP_CPCI_RSRCCTL 0x0b
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#define PCI_CAP_HOTPLUG 0x0c
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#define PCI_CAP_HOTPLUG 0x0c /* Standard Hot-Plug Controller(SHPC)*/
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#define PCI_CAP_SUBVENDOR 0x0d
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#define PCI_CAP_AGP8 0x0e
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#define PCI_CAP_SECURE 0x0f
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@ -597,6 +593,8 @@ typedef u_int8_t pci_revision_t;
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* Capability ID: 0x02
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* AGP
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*/
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#define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf)
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#define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf)
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/*
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* Capability ID: 0x03
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@ -1008,7 +1006,7 @@ typedef u_int8_t pci_revision_t;
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#define PCIE_DCAP2_NO_ROPR_PASS __BIT(10) /* No RO-enabled PR-PR Passng */
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#define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */
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#define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */
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#define PCIE_DCAP2_OBFF __BITS(19, 18) /* OBPF */
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#define PCIE_DCAP2_OBFF __BITS(19, 18) /* Optimized Buffer Flush/Fill*/
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#define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */
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#define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */
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#define PCIE_DCAP2_MAX_EETLP __BITS(23, 22) /* Max End-End TLP Prefix Sup */
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@ -1081,10 +1079,10 @@ struct pci_msix_table_entry {
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uint32_t pci_msix_value;
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uint32_t pci_msix_vector_control;
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};
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#define PCI_MSIX_VECTCTL_HWMASK_MASK 0x00000001
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#define PCI_MSIX_VECTCTL_MASK __BIT(0)
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/* Max number of MSI-X vectors. See PCI-SIG specification. */
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#define PCI_MSIX_MAX_VECTORS 2048
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#define PCI_MSIX_MAX_VECTORS 2048
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/*
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* Capability ID: 0x12
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@ -1103,11 +1101,11 @@ struct pci_msix_table_entry {
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* Capability ID: 0x13
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* Advanced Feature
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*/
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#define PCI_AFCAPR 0x00 /* Capabilities */
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#define PCI_AFCAPR 0x00 /* Capabilities */
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#define PCI_AFCAPR_MASK __BITS(31, 24)
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#define PCI_AF_TP_CAP __BIT(24) /* Transaction Pending */
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#define PCI_AF_FLR_CAP __BIT(25) /* Function Level Reset */
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#define PCI_AFCSR 0x04 /* Control & Status register */
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#define PCI_AFCSR 0x04 /* Control & Status register */
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#define PCI_AFCR_INITIATE_FLR __BIT(0) /* Initiate Function LVL RST */
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#define PCI_AFSR_TP __BIT(8) /* Transaction Pending */
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@ -1368,7 +1366,7 @@ struct pci_rom {
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#define PCI_EXTCAP_MCAST 0x0012 /* Multicast */
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#define PCI_EXTCAP_PAGE_REQ 0x0013 /* Page Request */
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#define PCI_EXTCAP_AMD 0x0014 /* Reserved for AMD */
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#define PCI_EXTCAP_RESIZE_BAR 0x0015 /* Resizable BAR */
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#define PCI_EXTCAP_RESIZ_BAR 0x0015 /* Resizable BAR */
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#define PCI_EXTCAP_DPA 0x0016 /* Dynamic Power Allocation */
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#define PCI_EXTCAP_TPH_REQ 0x0017 /* TPH Requester */
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#define PCI_EXTCAP_LTR 0x0018 /* Latency Tolerance Reporting */
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@ -1388,7 +1386,7 @@ struct pci_rom {
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* Extended capability ID: 0x0001
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* Advanced Error Reporting
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*/
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#define PCI_AER_UC_STATUS 0x04 /* Uncorrectable Error Status Register */
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#define PCI_AER_UC_STATUS 0x04 /* Uncorrectable Error Status Reg. */
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#define PCI_AER_UC_UNDEFINED __BIT(0)
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#define PCI_AER_UC_DL_PROTOCOL_ERROR __BIT(4)
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#define PCI_AER_UC_SURPRISE_DOWN_ERROR __BIT(5)
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@ -1408,7 +1406,7 @@ struct pci_rom {
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#define PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR __BIT(25)
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#define PCI_AER_UC_MASK 0x08 /* Uncorrectable Error Mask Register */
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/* Shares bits with UC_STATUS */
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#define PCI_AER_UC_SEVERITY 0x0c /* Uncorrectable Error Severity Register */
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#define PCI_AER_UC_SEVERITY 0x0c /* Uncorrectable Error Severity Reg. */
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/* Shares bits with UC_STATUS */
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#define PCI_AER_COR_STATUS 0x10 /* Correctable Error Status Register */
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#define PCI_AER_COR_RECEIVER_ERROR __BIT(0)
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@ -1421,7 +1419,7 @@ struct pci_rom {
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#define PCI_AER_COR_HEADER_LOG_OVERFLOW __BIT(15)
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#define PCI_AER_COR_MASK 0x14 /* Correctable Error Mask Register */
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/* Shares bits with COR_STATUS */
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#define PCI_AER_CAP_CONTROL 0x18 /* Advanced Error Capabilities and Control Register */
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#define PCI_AER_CAP_CONTROL 0x18 /* AE Capabilities and Control Reg. */
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#define PCI_AER_FIRST_ERROR_PTR __BITS(4, 0)
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#define PCI_AER_FIRST_ERROR_PTR_S 0
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#define PCI_AER_FIRST_ERROR_PTR_M 0x1f
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