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Add Precision Time Management (PTM) ECN.

This commit is contained in:
msaitoh 2016-05-11 05:12:57 +00:00
parent 9ea1e5fd3d
commit 20025a8603
2 changed files with 84 additions and 5 deletions
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53
sys/dev/pci/pci_subr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pci_subr.c,v 1.146 2015/11/18 04:24:02 msaitoh Exp $ */
/* $NetBSD: pci_subr.c,v 1.147 2016/05/11 05:12:57 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.146 2015/11/18 04:24:02 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.147 2016/05/11 05:12:57 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@ -3233,7 +3233,52 @@ pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff)
printf("%dus\n", val * scale);
}
/* XXX pci_conf_print_ptm_cap */
static void
pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff)
{
pcireg_t reg;
uint32_t val;
printf("\n Precision Time Management\n");
reg = regs[o2i(extcapoff + PCI_PTM_CAP)];
printf(" PTM Capability register: 0x%08x\n", reg);
onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ);
onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP);
onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT);
printf(" Local Clock Granularity: ");
val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL);
switch (val) {
case 0:
printf("Not implemented\n");
break;
case 0xffff:
printf("> 254ns\n");
break;
default:
printf("%uns\n", val);
break;
}
reg = regs[o2i(extcapoff + PCI_PTM_CTL)];
printf(" PTM Control register: 0x%08x\n", reg);
onoff("PTM Enable", reg, PCI_PTM_CTL_EN);
onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL);
printf(" Effective Granularity: ");
val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL);
switch (val) {
case 0:
printf("Unknown\n");
break;
case 0xffff:
printf("> 254ns\n");
break;
default:
printf("%uns\n", val);
break;
}
}
/* XXX pci_conf_print_mpcie_cap */
/* XXX pci_conf_print_frsq_cap */
/* XXX pci_conf_print_rtr_cap */
@ -3311,7 +3356,7 @@ static struct {
{ PCI_EXTCAP_L1PM, "L1 PM Substates",
pci_conf_print_l1pm_cap },
{ PCI_EXTCAP_PTM, "Precision Time Management",
NULL },
pci_conf_print_ptm_cap },
{ PCI_EXTCAP_MPCIE, "M-PCIe",
NULL },
{ PCI_EXTCAP_FRSQ, "Function Reading Status Queueing",

36
sys/dev/pci/pcireg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pcireg.h,v 1.112 2015/11/18 04:24:02 msaitoh Exp $ */
/* $NetBSD: pcireg.h,v 1.113 2016/05/11 05:12:57 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@ -1890,4 +1890,38 @@ struct pci_rom {
#define PCI_L1PM_CTL2_TPOSCALE __BITS(1, 0) /* T_POWER_ON Scale */
#define PCI_L1PM_CTL2_TPOVAL __BITS(7, 3) /* T_POWER_ON Value */
/*
* Extended capability ID: 0x001f
* Precision Time Management
*/
#define PCI_PTM_CAP 0x04 /* Capabilities Register */
#define PCI_PTM_CAP_REQ __BIT(0) /* PTM Requester Capable */
#define PCI_PTM_CAP_RESP __BIT(1) /* PTM Responder Capable */
#define PCI_PTM_CAP_ROOT __BIT(2) /* PTM Root Capable */
#define PCI_PTM_CAP_LCLCLKGRNL __BITS(15, 8) /* Local Clock Granularity */
#define PCI_PTM_CTL 0x08 /* Control Register */
#define PCI_PTM_CTL_EN __BIT(0) /* PTM Enable */
#define PCI_PTM_CTL_ROOTSEL __BIT(1) /* Root Select */
#define PCI_PTM_CTL_EFCTGRNL __BITS(15, 8) /* Effective Granularity */
/*
* Extended capability ID: 0x0020
* M-PCIe
*/
/*
* Extended capability ID: 0x0021
* Function Reading Status Queueing
*/
/*
* Extended capability ID: 0x0022
* Readiness Time Reporting
*/
/*
* Extended capability ID: 0x0023
* Designated Vendor-Specific
*/
#endif /* _DEV_PCI_PCIREG_H_ */