- Add PCI-X capability stuff.
- remove extra ':' in pci_conf_print_pcie_cap() - Add comments.
This commit is contained in:
msaitoh
parent
b95787afbc
commit
486f844f78
@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.121 2014/05/27 16:50:31 msaitoh Exp $ */
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/* $NetBSD: pci_subr.c,v 1.122 2014/05/30 03:42:38 msaitoh Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.121 2014/05/27 16:50:31 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.122 2014/05/30 03:42:38 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_pci.h"
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@ -1117,7 +1117,109 @@ pci_conf_print_msi_cap(const pcireg_t *regs, int capoff)
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}
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/* XXX pci_conf_print_cpci_hostwap_cap */
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/* XXX pci_conf_print_pcix_cap */
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/*
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* For both command register and status register.
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* The argument "idx" is index number (0 to 7).
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*/
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static int
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pcix_split_trans(unsigned int idx)
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{
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static int table[8] = {
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1, 2, 3, 4, 8, 12, 16, 32
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};
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if (idx >= __arraycount(table))
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return -1;
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return table[idx];
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}
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static void
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pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff)
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{
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pcireg_t reg;
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int isbridge;
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int i;
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isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])
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& PCI_HDRTYPE_PPB) != 0 ? 1 : 0;
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printf("\n PCI-X %s Capabilities Register\n",
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isbridge ? "Bridge" : "Non-bridge");
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reg = regs[o2i(capoff)];
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if (isbridge != 0) {
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printf(" Secondary status register: 0x%04x\n",
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(reg & 0xffff0000) >> 16);
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onoff("64bit device", reg, PCIX_STATUS_64BIT);
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onoff("133MHz capable", reg, PCIX_STATUS_133);
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onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
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onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
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onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
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onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
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printf(" Secondary clock frequency: 0x%x\n",
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(reg & PCIX_BRIDGE_2NDST_CLKF)
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>> PCIX_BRIDGE_2NDST_CLKF_SHIFT);
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printf(" Version: 0x%x\n",
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(reg & PCIX_BRIDGE_2NDST_VER_MASK)
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>> PCIX_BRIDGE_2NDST_VER_SHIFT);
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onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266);
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onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533);
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} else {
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printf(" Command register: 0x%04x\n",
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(reg & 0xffff0000) >> 16);
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onoff("Data Parity Error Recovery", reg,
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PCIX_CMD_PERR_RECOVER);
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onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER);
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printf(" Maximum Burst Read Count: %u\n",
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PCIX_CMD_BYTECNT(reg));
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printf(" Maximum Split Transactions: %d\n",
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pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK)
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>> PCIX_CMD_SPLTRANS_SHIFT));
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}
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reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */
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printf(" %sStatus register: 0x%08x\n",
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isbridge ? "Bridge " : "", reg);
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printf(" Function: %d\n", PCIX_STATUS_FN(reg));
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printf(" Device: %d\n", PCIX_STATUS_DEV(reg));
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printf(" Bus: %d\n", PCIX_STATUS_BUS(reg));
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onoff("64bit device", reg, PCIX_STATUS_64BIT);
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onoff("133MHz capable", reg, PCIX_STATUS_133);
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onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
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onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
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if (isbridge != 0) {
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onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
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onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
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} else {
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onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX,
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"bridge device", "simple device");
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printf(" Designed max memory read byte count: %d\n",
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512 << ((reg & PCIX_STATUS_MAXB_MASK)
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>> PCIX_STATUS_MAXB_SHIFT));
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printf(" Designed max outstanding split transaction: %d\n",
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pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK)
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>> PCIX_STATUS_MAXST_SHIFT));
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printf(" MAX cumulative Read Size: %u\n",
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8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT));
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onoff("Received split completion error", reg,
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PCIX_STATUS_SCERR);
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}
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onoff("266MHz capable", reg, PCIX_STATUS_266);
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onoff("533MHz capable", reg, PCIX_STATUS_533);
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if (isbridge == 0)
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return;
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/* Only for bridge */
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for (i = 0; i < 2; i++) {
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reg = regs[o2i(capoff+PCIX_BRIDGE_UP_STCR + (4 * i))];
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printf(" %s split transaction control register: 0x%08x\n",
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(i == 0) ? "Upstream" : "Downstream", reg);
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printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP);
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printf(" Commitment Limit: %d\n",
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(reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT);
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}
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}
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/* XXX pci_conf_print_ldt_cap */
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/* XXX pci_conf_print_vendspec_cap */
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@ -1329,8 +1431,8 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6);
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printf(" Endpoint L1 Acceptable Latency: ");
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pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9);
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onoff("Attention Button Present:", reg, PCIE_DCAP_ATTN_BUTTON);
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onoff("Attention Indicator Present:", reg, PCIE_DCAP_ATTN_IND);
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onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON);
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onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND);
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onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND);
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onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT);
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printf(" Captured Slot Power Limit Value: %d\n",
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@ -1745,8 +1847,8 @@ pci_conf_print_caplist(
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{
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int off;
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pcireg_t rval;
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int pcie_off = -1, pcipm_off = -1, msi_off = -1, vendspec_off = -1;
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int msix_off = -1;
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int pcie_off = -1, pcipm_off = -1, msi_off = -1, pcix_off = -1;
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int vendspec_off = -1, msix_off = -1;
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int debugport_off = -1, subsystem_off = -1, pciaf_off = -1;
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for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
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@ -1784,6 +1886,7 @@ pci_conf_print_caplist(
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printf("CompactPCI Hot-swapping");
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break;
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case PCI_CAP_PCIX:
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pcix_off = off;
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printf("PCI-X");
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break;
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case PCI_CAP_LDT:
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@ -1841,7 +1944,8 @@ pci_conf_print_caplist(
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if (msi_off != -1)
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pci_conf_print_msi_cap(regs, msi_off);
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/* XXX CPCI_HOTSWAP */
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/* XXX PCIX */
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if (pcix_off != -1)
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pci_conf_print_pcix_cap(regs, pcix_off);
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/* XXX LDT */
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if (vendspec_off != -1)
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pci_conf_print_vendspec_cap(regs, vendspec_off);
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@ -1,4 +1,4 @@
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/* $NetBSD: pcireg.h,v 1.93 2014/05/27 16:26:15 msaitoh Exp $ */
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/* $NetBSD: pcireg.h,v 1.94 2014/05/30 03:42:38 msaitoh Exp $ */
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/*
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* Copyright (c) 1995, 1996, 1999, 2000
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@ -640,8 +640,14 @@ typedef u_int8_t pci_revision_t;
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/*
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* Capability ID: 0x07
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* PCI-X capability.
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*
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* PCI-X capability register has two different layouts. One is for bridge
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* function. Another is for non-bridge functions.
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*/
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/* For non-bridge functions */
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/*
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* Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit
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* word at the capability; the lower 16 bits are the capability ID and
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@ -651,21 +657,24 @@ typedef u_int8_t pci_revision_t;
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* as 32-bit values, offset and shifted appropriately. Make sure you perform
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* the appropriate R/M/W cycles!
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*/
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#define PCIX_CMD 0x00
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#define PCIX_CMD 0x00
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#define PCIX_CMD_PERR_RECOVER 0x00010000
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#define PCIX_CMD_RELAXED_ORDER 0x00020000
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#define PCIX_CMD_BYTECNT_MASK 0x000c0000
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#define PCIX_CMD_BYTECNT_SHIFT 18
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#define PCIX_CMD_BCNT_512 0x00000000
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#define PCIX_CMD_BCNT_1024 0x00040000
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#define PCIX_CMD_BCNT_2048 0x00080000
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#define PCIX_CMD_BCNT_4096 0x000c0000
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#define PCIX_CMD_BYTECNT(reg) \
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(512 << (((reg) & PCIX_CMD_BYTECNT_MASK) >> PCIX_CMD_BYTECNT_SHIFT))
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#define PCIX_CMD_BCNT_512 0x00000000
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#define PCIX_CMD_BCNT_1024 0x00040000
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#define PCIX_CMD_BCNT_2048 0x00080000
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#define PCIX_CMD_BCNT_4096 0x000c0000
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#define PCIX_CMD_SPLTRANS_MASK 0x00700000
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#define PCIX_CMD_SPLTRANS_1 0x00000000
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#define PCIX_CMD_SPLTRANS_2 0x00100000
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#define PCIX_CMD_SPLTRANS_3 0x00200000
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#define PCIX_CMD_SPLTRANS_4 0x00300000
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#define PCIX_CMD_SPLTRANS_8 0x00400000
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#define PCIX_CMD_SPLTRANS_SHIFT 20
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#define PCIX_CMD_SPLTRANS_1 0x00000000
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#define PCIX_CMD_SPLTRANS_2 0x00100000
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#define PCIX_CMD_SPLTRANS_3 0x00200000
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#define PCIX_CMD_SPLTRANS_4 0x00300000
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#define PCIX_CMD_SPLTRANS_8 0x00400000
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#define PCIX_CMD_SPLTRANS_12 0x00500000
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#define PCIX_CMD_SPLTRANS_16 0x00600000
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#define PCIX_CMD_SPLTRANS_32 0x00700000
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@ -673,31 +682,40 @@ typedef u_int8_t pci_revision_t;
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/*
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* Status. 32 bits at offset 4.
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*/
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#define PCIX_STATUS 0x04
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#define PCIX_STATUS_FN_MASK 0x00000007
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#define PCIX_STATUS 0x04
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#define PCIX_STATUS_FN_MASK 0x00000007
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#define PCIX_STATUS_DEV_MASK 0x000000f8
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#define PCIX_STATUS_DEV_SHIFT 3
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#define PCIX_STATUS_BUS_MASK 0x0000ff00
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#define PCIX_STATUS_64BIT 0x00010000
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#define PCIX_STATUS_133 0x00020000
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#define PCIX_STATUS_SPLDISC 0x00040000
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#define PCIX_STATUS_SPLUNEX 0x00080000
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#define PCIX_STATUS_DEVCPLX 0x00100000
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#define PCIX_STATUS_MAXB_MASK 0x00600000
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#define PCIX_STATUS_BUS_SHIFT 8
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#define PCIX_STATUS_FN(val) ((val) & PCIX_STATUS_FN_MASK)
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#define PCIX_STATUS_DEV(val) \
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(((val) & PCIX_STATUS_DEV_MASK) >> PCIX_STATUS_DEV_SHIFT)
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#define PCIX_STATUS_BUS(val) \
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(((val) & PCIX_STATUS_BUS_MASK) >> PCIX_STATUS_BUS_SHIFT)
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#define PCIX_STATUS_64BIT 0x00010000 /* 64bit device */
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#define PCIX_STATUS_133 0x00020000 /* 133MHz capable */
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#define PCIX_STATUS_SPLDISC 0x00040000 /* Split completion discarded*/
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#define PCIX_STATUS_SPLUNEX 0x00080000 /* Unexpected split complet. */
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#define PCIX_STATUS_DEVCPLX 0x00100000 /* Device Complexity */
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#define PCIX_STATUS_MAXB_MASK 0x00600000 /* MAX memory read Byte count*/
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#define PCIX_STATUS_MAXB_SHIFT 21
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#define PCIX_STATUS_MAXB_512 0x00000000
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#define PCIX_STATUS_MAXB_1024 0x00200000
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#define PCIX_STATUS_MAXB_2048 0x00400000
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#define PCIX_STATUS_MAXB_4096 0x00600000
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#define PCIX_STATUS_MAXST_MASK 0x03800000
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#define PCIX_STATUS_MAXST_1 0x00000000
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#define PCIX_STATUS_MAXST_2 0x00800000
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#define PCIX_STATUS_MAXST_3 0x01000000
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#define PCIX_STATUS_MAXST_4 0x01800000
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#define PCIX_STATUS_MAXST_8 0x02000000
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#define PCIX_STATUS_MAXST_MASK 0x03800000 /* MAX outstand. Split Trans.*/
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#define PCIX_STATUS_MAXST_SHIFT 23
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#define PCIX_STATUS_MAXST_1 0x00000000
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#define PCIX_STATUS_MAXST_2 0x00800000
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#define PCIX_STATUS_MAXST_3 0x01000000
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#define PCIX_STATUS_MAXST_4 0x01800000
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#define PCIX_STATUS_MAXST_8 0x02000000
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#define PCIX_STATUS_MAXST_12 0x02800000
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#define PCIX_STATUS_MAXST_16 0x03000000
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#define PCIX_STATUS_MAXST_32 0x03800000
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#define PCIX_STATUS_MAXRS_MASK 0x1c000000
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#define PCIX_STATUS_MAXRS_MASK 0x1c000000 /* MAX cumulative Read Size */
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#define PCIX_STATUS_MAXRS_SHIFT 26
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#define PCIX_STATUS_MAXRS_1K 0x00000000
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#define PCIX_STATUS_MAXRS_2K 0x04000000
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#define PCIX_STATUS_MAXRS_4K 0x08000000
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@ -706,7 +724,37 @@ typedef u_int8_t pci_revision_t;
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#define PCIX_STATUS_MAXRS_32K 0x14000000
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#define PCIX_STATUS_MAXRS_64K 0x18000000
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#define PCIX_STATUS_MAXRS_128K 0x1c000000
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#define PCIX_STATUS_SCERR 0x20000000
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#define PCIX_STATUS_SCERR 0x20000000 /* rcv. Split Completion ERR.*/
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#define PCIX_STATUS_266 0x40000000 /* 266MHz capable */
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#define PCIX_STATUS_533 0x80000000 /* 533MHz capable */
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/* For bridge function */
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#define PCIX_BRIDGE_2ND_STATUS 0x00
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#define PCIX_BRIDGE_ST_64BIT 0x00010000 /* Same as PCIX_STATUS (nonb)*/
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#define PCIX_BRIDGE_ST_133 0x00020000 /* Same as PCIX_STATUS (nonb)*/
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#define PCIX_BRIDGE_ST_SPLDISC 0x00040000 /* Same as PCIX_STATUS (nonb)*/
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#define PCIX_BRIDGE_ST_SPLUNEX 0x00080000 /* Same as PCIX_STATUS (nonb)*/
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#define PCIX_BRIDGE_ST_SPLOVRN 0x00100000 /* Split completion overrun */
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#define PCIX_BRIDGE_ST_SPLRQDL 0x00200000 /* Split request delayed */
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#define PCIX_BRIDGE_2NDST_CLKF 0x03c00000 /* Secondary clock frequency */
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#define PCIX_BRIDGE_2NDST_CLKF_SHIFT 22
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#define PCIX_BRIDGE_2NDST_VER_MASK 0x30000000 /* Version */
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#define PCIX_BRIDGE_2NDST_VER_SHIFT 28
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#define PCIX_BRIDGE_ST_266 0x40000000 /* Same as PCIX_STATUS (nonb)*/
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#define PCIX_BRIDGE_ST_533 0x80000000 /* Same as PCIX_STATUS (nonb)*/
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#define PCIX_BRIDGE_PRI_STATUS 0x04
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/* Bit 0 to 15 are the same as PCIX_STATUS */
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/* Bit 16 to 21 are the same as PCIX_BRIDGE_2ND_STATUS */
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/* Bit 30 and 31 are the same as PCIX_BRIDGE_2ND_STATUS */
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#define PCIX_BRIDGE_UP_STCR 0x08 /* Upstream Split Transaction Control */
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#define PCIX_BRIDGE_DOWN_STCR 0x0c /* Downstream Split Transaction Control */
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/* The layouts of above two registers are the same */
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#define PCIX_BRIDGE_STCAP 0x0000ffff /* Sp. Tr. Capacity */
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#define PCIX_BRIDGE_STCLIM 0xffff0000 /* Sp. Tr. Commitment Limit */
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#define PCIX_BRIDGE_STCLIM_SHIFT 16
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/*
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* Capability ID: 0x08
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