- Print PCIe 2.0 or higher capability registers.
- Print Link related registers only if the device is PCI Express Endpoint, Legacy PCI Express Endpoint or Root Port of PCI Express Root Complex. - Don't print Root related registers if the device is Root Complex Integrated Endpoint and print if the device is Root Complex Event Collector. - Not Gb/s but GT/s.
This commit is contained in:
msaitoh
parent
956c0afde5
commit
1a2c729863
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.104 2013/04/21 23:46:06 msaitoh Exp $ */
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/* $NetBSD: pci_subr.c,v 1.105 2013/04/21 23:54:44 msaitoh Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.104 2013/04/21 23:46:06 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.105 2013/04/21 23:54:44 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_pci.h"
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@ -856,33 +856,65 @@ pci_print_pcie_L1_latency(uint32_t val)
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}
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}
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static void
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pci_print_pcie_compl_timeout(uint32_t val)
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{
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switch (val) {
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case 0x0:
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printf("50us to 50ms\n");
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break;
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case 0x5:
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printf("16ms to 55ms\n");
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break;
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case 0x6:
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printf("65ms to 210ms\n");
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break;
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case 0x9:
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printf("260ms to 900ms\n");
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break;
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case 0xa:
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printf("1s to 3.5s\n");
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break;
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default:
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printf("unknown %u value\n", val);
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break;
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}
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}
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static void
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pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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{
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pcireg_t reg; /* for each register */
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pcireg_t val; /* for each bitfield */
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bool check_link = false;
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bool check_slot = false;
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bool check_rootport = false;
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unsigned int pciever;
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static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"};
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int i;
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printf("\n PCI Express Capabilities Register\n");
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/* Capability Register */
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reg = regs[o2i(capoff)];
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printf(" Capability register: %04x\n", reg >> 16);
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printf(" Capability version: %x\n",
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(unsigned int)((reg & 0x000f0000) >> 16));
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pciever = (unsigned int)((reg & 0x000f0000) >> 16);
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printf(" Capability version: %u\n", pciever);
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printf(" Device type: ");
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switch ((reg & 0x00f00000) >> 20) {
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case 0x0:
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printf("PCI Express Endpoint device\n");
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check_link = true;
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break;
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case 0x1:
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printf("Legacy PCI Express Endpoint device\n");
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check_link = true;
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break;
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case 0x4:
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printf("Root Port of PCI Express Root Complex\n");
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check_link = true;
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check_slot = true;
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check_rootport = true; /* XXX right? */
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check_rootport = true;
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break;
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case 0x5:
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printf("Upstream Port of PCI Express Switch\n");
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@ -890,7 +922,7 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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case 0x6:
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printf("Downstream Port of PCI Express Switch\n");
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check_slot = true;
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check_rootport = true; /* XXX right? */
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check_rootport = true;
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break;
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case 0x7:
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printf("PCI Express to PCI/PCI-X Bridge\n");
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@ -900,9 +932,9 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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break;
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case 0x9:
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printf("Root Complex Integrated Endpoint\n");
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check_rootport = true; /* XXX right? */
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break;
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case 0xa:
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check_rootport = true;
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printf("Root Complex Event Collector\n");
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break;
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default:
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@ -997,103 +1029,104 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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printf(" Transaction Pending: %s\n",
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(reg & PCIE_DCSR_TRANSACTION_PND) != 0 ? "on" : "off");
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/* Link Capability Register */
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reg = regs[o2i(capoff + PCIE_LCAP)];
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printf(" Link Capabilities Register: 0x%08x\n", reg);
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printf(" Maximum Link Speed: ");
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val = reg & PCIE_LCAP_MAX_SPEED;
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if (val < 1 || val > 3) {
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printf("unknown %u value\n", val);
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} else {
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printf("%sGb/s\n", linkspeeds[val - 1]);
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}
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printf(" Maximum Link Width: x%u lanes\n",
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(unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4);
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printf(" Active State PM Support: ");
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val = (reg & PCIE_LCAP_ASPM) >> 10;
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switch (val) {
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case 0x1:
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printf("L0s Entry supported\n");
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break;
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case 0x3:
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printf("L0s and L1 supported\n");
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break;
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default:
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printf("Reserved value\n");
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break;
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}
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printf(" L0 Exit Latency: ");
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pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12);
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printf(" L1 Exit Latency: ");
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pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15);
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printf(" Port Number: %u\n", reg >> 24);
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if (check_link) {
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/* Link Capability Register */
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reg = regs[o2i(capoff + PCIE_LCAP)];
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printf(" Link Capabilities Register: 0x%08x\n", reg);
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printf(" Maximum Link Speed: ");
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val = reg & PCIE_LCAP_MAX_SPEED;
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if (val < 1 || val > 3) {
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printf("unknown %u value\n", val);
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} else {
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printf("%sGT/s\n", linkspeeds[val - 1]);
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}
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printf(" Maximum Link Width: x%u lanes\n",
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(unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4);
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printf(" Active State PM Support: ");
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val = (reg & PCIE_LCAP_ASPM) >> 10;
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switch (val) {
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case 0x1:
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printf("L0s Entry supported\n");
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break;
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case 0x3:
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printf("L0s and L1 supported\n");
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break;
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default:
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printf("Reserved value\n");
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break;
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}
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printf(" L0 Exit Latency: ");
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pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12);
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printf(" L1 Exit Latency: ");
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pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15);
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printf(" Port Number: %u\n", reg >> 24);
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/* Link Control Register */
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reg = regs[o2i(capoff + PCIE_LCSR)];
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printf(" Link Control Register: 0x%04x\n", reg & 0xffff);
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printf(" Active State PM Control: ");
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val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S);
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switch (val) {
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case 0:
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printf("disabled\n");
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break;
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case 1:
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printf("L0s Entry Enabled\n");
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break;
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case 2:
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printf("L1 Entry Enabled\n");
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break;
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case 3:
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printf("L0s and L1 Entry Enabled\n");
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break;
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}
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printf(" Read Completion Boundary Control: %dbyte\n",
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(reg & PCIE_LCSR_RCB) != 0 ? 128 : 64);
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printf(" Link Disable: %s\n",
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(reg & PCIE_LCSR_LINK_DIS) != 0 ? "on" : "off");
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printf(" Retrain Link: %s\n",
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(reg & PCIE_LCSR_RETRAIN) != 0 ? "on" : "off");
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printf(" Common Clock Configuration: %s\n",
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(reg & PCIE_LCSR_COMCLKCFG) != 0 ? "on" : "off");
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printf(" Extended Synch: %s\n",
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(reg & PCIE_LCSR_EXTNDSYNC) != 0 ? "on" : "off");
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printf(" Enable Clock Power Management: %s\n",
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(reg & PCIE_LCSR_ENCLKPM) != 0 ? "on" : "off");
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printf(" Hardware Autonomous Width Disable: %s\n",
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(reg & PCIE_LCSR_HAWD) != 0 ? "on" : "off");
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printf(" Link Bandwidth Management Interrupt Enable: %s\n",
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(reg & PCIE_LCSR_LBMIE) != 0 ? "on" : "off");
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printf(" Link Autonomous Bandwidth Interrupt Enable: %s\n",
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(reg & PCIE_LCSR_LABIE) != 0 ? "on" : "off");
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/* Link Control Register */
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reg = regs[o2i(capoff + PCIE_LCSR)];
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printf(" Link Control Register: 0x%04x\n", reg & 0xffff);
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printf(" Active State PM Control: ");
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val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S);
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switch (val) {
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case 0:
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printf("disabled\n");
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break;
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case 1:
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printf("L0s Entry Enabled\n");
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break;
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case 2:
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printf("L1 Entry Enabled\n");
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break;
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case 3:
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printf("L0s and L1 Entry Enabled\n");
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break;
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}
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printf(" Read Completion Boundary Control: %dbyte\n",
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(reg & PCIE_LCSR_RCB) != 0 ? 128 : 64);
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printf(" Link Disable: %s\n",
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(reg & PCIE_LCSR_LINK_DIS) != 0 ? "on" : "off");
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printf(" Retrain Link: %s\n",
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(reg & PCIE_LCSR_RETRAIN) != 0 ? "on" : "off");
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printf(" Common Clock Configuration: %s\n",
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(reg & PCIE_LCSR_COMCLKCFG) != 0 ? "on" : "off");
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printf(" Extended Synch: %s\n",
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(reg & PCIE_LCSR_EXTNDSYNC) != 0 ? "on" : "off");
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printf(" Enable Clock Power Management: %s\n",
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(reg & PCIE_LCSR_ENCLKPM) != 0 ? "on" : "off");
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printf(" Hardware Autonomous Width Disable: %s\n",
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(reg & PCIE_LCSR_HAWD) != 0 ? "on" : "off");
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printf(" Link Bandwidth Management Interrupt Enable: %s\n",
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(reg & PCIE_LCSR_LBMIE) != 0 ? "on" : "off");
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printf(" Link Autonomous Bandwidth Interrupt Enable: %s\n",
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(reg & PCIE_LCSR_LABIE) != 0 ? "on" : "off");
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/* Link Status Register */
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reg = regs[o2i(capoff + PCIE_LCSR)];
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printf(" Link Status Register: 0x%04x\n", reg >> 16);
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printf(" Negotiated Link Speed: ");
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if (((reg >> 16) & 0x000f) < 1 ||
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((reg >> 16) & 0x000f) > 3) {
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printf("unknown %u value\n",
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(unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16);
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} else {
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printf("%sGb/s\n",
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linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16) - 1]);
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/* Link Status Register */
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reg = regs[o2i(capoff + PCIE_LCSR)];
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printf(" Link Status Register: 0x%04x\n", reg >> 16);
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printf(" Negotiated Link Speed: ");
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if (((reg >> 16) & 0x000f) < 1 ||
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((reg >> 16) & 0x000f) > 3) {
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printf("unknown %u value\n",
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(unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16);
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} else {
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printf("%sGb/s\n",
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linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16) - 1]);
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}
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printf(" Negotiated Link Width: x%u lanes\n",
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(reg >> 20) & 0x003f);
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printf(" Training Error: %s\n",
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(reg & PCIE_LCSR_LINKTRAIN_ERR) != 0 ? "on" : "off");
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printf(" Link Training: %s\n",
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(reg & PCIE_LCSR_LINKTRAIN) != 0 ? "on" : "off");
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printf(" Slot Clock Configuration: %s\n",
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(reg & PCIE_LCSR_SLOTCLKCFG) != 0 ? "on" : "off");
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printf(" Data Link Layer Link Active: %s\n",
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(reg & PCIE_LCSR_DLACTIVE) != 0 ? "on" : "off");
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printf(" Link Bandwidth Management Status: %s\n",
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(reg & PCIE_LCSR_LINK_BW_MGMT) != 0 ? "on" : "off");
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printf(" Link Autonomous Bandwidth Status: %s\n",
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(reg & PCIE_LCSR_LINK_AUTO_BW) != 0 ? "on" : "off");
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}
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printf(" Negotiated Link Width: x%u lanes\n",
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(reg >> 20) & 0x003f);
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printf(" Training Error: %s\n",
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(reg & PCIE_LCSR_LINKTRAIN_ERR) != 0 ? "on" : "off");
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printf(" Link Training: %s\n",
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(reg & PCIE_LCSR_LINKTRAIN) != 0 ? "on" : "off");
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printf(" Slot Clock Configuration: %s\n",
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(reg & PCIE_LCSR_SLOTCLKCFG) != 0 ? "on" : "off");
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printf(" Data Link Layer Link Active: %s\n",
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(reg & PCIE_LCSR_DLACTIVE) != 0 ? "on" : "off");
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printf(" Link Bandwidth Management Status: %s\n",
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(reg & PCIE_LCSR_LINK_BW_MGMT) != 0 ? "on" : "off");
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printf(" Link Autonomous Bandwidth Status: %s\n",
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(reg & PCIE_LCSR_LINK_AUTO_BW) != 0 ? "on" : "off");
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/* XXX Is this check right? */
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if (check_slot == true) {
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/* Slot Capability Register */
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reg = regs[o2i(capoff + PCIE_SLCAP)];
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@ -1200,7 +1233,6 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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printf(" Data Link Layer State Changed\n");
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}
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/* XXX Is this check right? */
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if (check_rootport == true) {
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/* Root Control Register */
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reg = regs[o2i(capoff + PCIE_RCR)];
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@ -1228,6 +1260,148 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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if ((reg & PCIE_RSR_PME_PEND) != 0)
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printf(" another PME is pending\n");
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}
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/* PCIe DW9 to DW14 is for PCIe 2.0 and newer */
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if (pciever < 2)
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return;
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/* Device Capabilities 2 */
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reg = regs[o2i(capoff + PCIE_DCAP2)];
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printf(" Device Capabilities 2: 0x%08x\n", reg);
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printf(" Completion Timeout Ranges Supported: %u \n",
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(unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE));
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printf(" Completion Timeout Disable Supported: %s\n",
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(reg & PCIE_DCAP2_COMPT_DIS) != 0 ? "yes" : "no");
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printf(" ARI Forwarding Supported: %s\n",
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(reg & PCIE_DCAP2_ARI_FWD) != 0 ? "yes" : "no");
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printf(" AtomicOp Routing Supported: %s\n",
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(reg & PCIE_DCAP2_ATOM_ROUT) != 0 ? "yes" : "no");
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printf(" 32bit AtomicOp Completer Supported: %s\n",
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(reg & PCIE_DCAP2_32ATOM) != 0 ? "yes" : "no");
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printf(" 64bit AtomicOp Completer Supported: %s\n",
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(reg & PCIE_DCAP2_64ATOM) != 0 ? "yes" : "no");
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printf(" 128-bit CAS Completer Supported: %s\n",
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(reg & PCIE_DCAP2_128CAS) != 0 ? "yes" : "no");
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printf(" No RO-enabled PR-PR passing: %s\n",
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(reg & PCIE_DCAP2_NO_ROPR_PASS) != 0 ? "yes" : "no");
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printf(" LTR Mechanism Supported: %s\n",
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(reg & PCIE_DCAP2_LTR_MEC) != 0 ? "yes" : "no");
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printf(" TPH Completer Supported: %u\n",
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(unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12);
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printf(" OBFF Supported: ");
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switch ((reg & PCIE_DCAP2_OBFF) >> 18) {
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case 0x0:
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printf("Not supported\n");
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break;
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case 0x1:
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printf("Message only\n");
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break;
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case 0x2:
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printf("WAKE# only\n");
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break;
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case 0x3:
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printf("Both\n");
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break;
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}
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printf(" Extended Fmt Field Supported: %s\n",
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(reg & PCIE_DCAP2_EXTFMT_FLD) != 0 ? "yes" : "no");
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printf(" End-End TLP Prefix Supported: %s\n",
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(reg & PCIE_DCAP2_EETLP_PREF) != 0 ? "yes" : "no");
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printf(" Max End-End TLP Prefixes: %u\n",
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(unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22);
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/* Device Control 2 */
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reg = regs[o2i(capoff + PCIE_DCSR2)];
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printf(" Device Control 2: 0x%04x\n", reg & 0xffff);
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printf(" Completion Timeout Value: ");
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pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL);
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if ((reg & PCIE_DCSR2_COMPT_DIS) != 0)
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printf(" Completion Timeout Disabled\n");
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if ((reg & PCIE_DCSR2_ARI_FWD) != 0)
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printf(" ARI Forwarding Enabled\n");
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if ((reg & PCIE_DCSR2_ATOM_REQ) != 0)
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printf(" AtomicOp Rquester Enabled\n");
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if ((reg & PCIE_DCSR2_ATOM_EBLK) != 0)
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printf(" AtomicOp Egress Blocking on\n");
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if ((reg & PCIE_DCSR2_IDO_REQ) != 0)
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printf(" IDO Request Enabled\n");
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if ((reg & PCIE_DCSR2_IDO_COMP) != 0)
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printf(" IDO Completion Enabled\n");
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if ((reg & PCIE_DCSR2_LTR_MEC) != 0)
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printf(" LTR Mechanism Enabled\n");
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printf(" OBFF: ");
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switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) {
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case 0x0:
|
||||
printf("Disabled\n");
|
||||
break;
|
||||
case 0x1:
|
||||
printf("Enabled with Message Signaling Variation A\n");
|
||||
break;
|
||||
case 0x2:
|
||||
printf("Enabled with Message Signaling Variation B\n");
|
||||
break;
|
||||
case 0x3:
|
||||
printf("Enabled using WAKE# signaling\n");
|
||||
break;
|
||||
}
|
||||
if ((reg & PCIE_DCSR2_EETLP) != 0)
|
||||
printf(" End-End TLP Prefix Blocking on\n");
|
||||
|
||||
if (check_link) {
|
||||
/* Link Capability 2 */
|
||||
reg = regs[o2i(capoff + PCIE_LCAP2)];
|
||||
printf(" Link Capabilities 2: 0x%08x\n", reg);
|
||||
val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1;
|
||||
printf(" Supported Link Speed Vector:");
|
||||
for (i = 0; i <= 2; i++) {
|
||||
if (((val >> i) & 0x01) != 0)
|
||||
printf(" %sGT/s", linkspeeds[i]);
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
/* Link Control 2 */
|
||||
reg = regs[o2i(capoff + PCIE_LCSR2)];
|
||||
printf(" Link Control 2: 0x%04x\n", reg & 0xffff);
|
||||
printf(" Target Link Speed: ");
|
||||
val = reg & PCIE_LCSR2_TGT_LSPEED;
|
||||
if (val < 1 || val > 3) {
|
||||
printf("unknown %u value\n", val);
|
||||
} else {
|
||||
printf("%sGT/s\n", linkspeeds[val - 1]);
|
||||
}
|
||||
if ((reg & PCIE_LCSR2_ENT_COMPL) != 0)
|
||||
printf(" Enter Compliance Enabled\n");
|
||||
if ((reg & PCIE_LCSR2_HW_AS_DIS) != 0)
|
||||
printf(" HW Autonomous Speed Disabled\n");
|
||||
if ((reg & PCIE_LCSR2_SEL_DEEMP) != 0)
|
||||
printf(" Selectable De-emphasis\n");
|
||||
printf(" Transmit Margin: %u\n",
|
||||
(unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7);
|
||||
if ((reg & PCIE_LCSR2_EN_MCOMP) != 0)
|
||||
printf(" Enter Modified Compliance\n");
|
||||
if ((reg & PCIE_LCSR2_COMP_SOS) != 0)
|
||||
printf(" Compliance SOS\n");
|
||||
printf(" Compliance Present/De-emphasis: %u\n",
|
||||
(unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12);
|
||||
|
||||
/* Link Status 2 */
|
||||
if ((reg & PCIE_LCSR2_DEEMP_LVL) != 0)
|
||||
printf(" Current De-emphasis Level\n");
|
||||
if ((reg & PCIE_LCSR2_EQ_COMPL) != 0)
|
||||
printf(" Equalization Complete\n");
|
||||
if ((reg & PCIE_LCSR2_EQP1_SUC) != 0)
|
||||
printf(" Equalization Phase 1 Successful\n");
|
||||
if ((reg & PCIE_LCSR2_EQP2_SUC) != 0)
|
||||
printf(" Equalization Phase 2 Successful\n");
|
||||
if ((reg & PCIE_LCSR2_EQP3_SUC) != 0)
|
||||
printf(" Equalization Phase 3 Successful\n");
|
||||
if ((reg & PCIE_LCSR2_LNKEQ_REQ) != 0)
|
||||
printf(" Link Equalization Request\n");
|
||||
}
|
||||
|
||||
/* Slot Capability 2 */
|
||||
/* Slot Control 2 */
|
||||
/* Slot Status 2 */
|
||||
}
|
||||
|
||||
static const char *
|
||||
|
|
|
|||
Loading…
Reference in New Issue