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Print the CRS Software Visibility Enable bit and the Crosslink Supported bit.

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This commit is contained in:
msaitoh 2014-05-09 14:51:26 +00:00
parent 1f04c0df66
commit 97e85871e2
2 changed files with 8 additions and 3 deletions
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8
sys/dev/pci/pci_subr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pci_subr.c,v 1.106 2013/08/05 07:53:31 msaitoh Exp $ */
/* $NetBSD: pci_subr.c,v 1.107 2014/05/09 14:51:26 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.106 2013/08/05 07:53:31 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.107 2014/05/09 14:51:26 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@ -1245,6 +1245,8 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
printf(" SERR on Fatal Error Enable\n");
if ((reg & PCIE_RCR_PME_IE) != 0)
printf(" PME Interrupt Enable\n");
if ((reg & PCIE_RCR_CRS_SVE) != 0)
printf(" CRS Software Visibility Enable\n");
/* Root Capability Register */
printf(" Root Capability Register: %04x\n",
@ -1357,6 +1359,8 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
if (((val >> i) & 0x01) != 0)
printf(" %sGT/s", linkspeeds[i]);
}
printf(" Crosslink Supported: %s\n",
(reg & PCIE_LCAP2_CROSSLNK) != 0 ? "yes" : "no");
printf("\n");
/* Link Control 2 */

3
sys/dev/pci/pcireg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pcireg.h,v 1.85 2014/03/29 19:28:25 christos Exp $ */
/* $NetBSD: pcireg.h,v 1.86 2014/05/09 14:51:26 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@ -751,6 +751,7 @@ struct pci_msix_table_entry {
#define PCIE_RCR_SERR_NFER __BIT(1) /* SERR on Non-Fatal Error En */
#define PCIE_RCR_SERR_FER __BIT(2) /* SERR on Fatal Error Enable */
#define PCIE_RCR_PME_IE __BIT(3) /* PME Interrupt Enable */
#define PCIE_RCR_CRS_SVE __BIT(4) /* CRS Software Visibility En */
#define PCIE_RSR 0x20 /* Root Status Register */
#define PCIE_RSR_PME_REQESTER __BITS(15, 0) /* PME Requester ID */
#define PCIE_RSR_PME_STAT __BIT(16) /* PME Status */