No functional change:
- KNF - Sort in PCI capability ID order. - Add comments.
This commit is contained in:
msaitoh
parent
79cab7f409
commit
310e8863ad
@ -1,4 +1,4 @@
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/* $NetBSD: pci_subr.c,v 1.114 2014/05/23 18:32:13 msaitoh Exp $ */
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/* $NetBSD: pci_subr.c,v 1.115 2014/05/23 19:31:23 msaitoh Exp $ */
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/*
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* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.114 2014/05/23 18:32:13 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.115 2014/05/23 19:31:23 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_pci.h"
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@ -148,14 +148,14 @@ static const struct pci_class pci_subclass_bridge[] = {
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};
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static const struct pci_class pci_subclass_communications[] = {
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{ "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, },
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{ "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, },
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{ "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, },
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{ "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, },
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{ "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, },
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{ "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, },
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{ "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, },
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{ NULL, 0, NULL, },
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{ "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL,},
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{ "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL,},
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{ "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,},
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{ "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL,},
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{ "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,},
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{ "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,},
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{ "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,},
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{ NULL, 0, NULL,},
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};
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static const struct pci_class pci_subclass_system[] = {
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@ -326,14 +326,18 @@ int pciverbose_loaded = 0;
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/*
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* Routine to load the pciverbose kernel module as needed
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*/
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void pci_load_verbose(void)
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void
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pci_load_verbose(void)
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{
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if (pciverbose_loaded == 0)
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module_autoload("pciverbose", MODULE_CLASS_MISC);
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}
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const char *pci_findvendor_stub(pcireg_t id_reg)
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const char *
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pci_findvendor_stub(pcireg_t id_reg)
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{
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pci_load_verbose();
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if (pciverbose_loaded)
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return pci_findvendor(id_reg);
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@ -341,8 +345,10 @@ const char *pci_findvendor_stub(pcireg_t id_reg)
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return NULL;
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}
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const char *pci_findproduct_stub(pcireg_t id_reg)
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const char *
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pci_findproduct_stub(pcireg_t id_reg)
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{
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pci_load_verbose();
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if (pciverbose_loaded)
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return pci_findproduct(id_reg);
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@ -505,15 +511,19 @@ pci_conf_print_common(
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onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE);
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onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE);
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onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE);
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onoff("Fast back-to-back transactions", rval, PCI_COMMAND_BACKTOBACK_ENABLE);
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onoff("Fast back-to-back transactions", rval,
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PCI_COMMAND_BACKTOBACK_ENABLE);
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onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE);
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printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff);
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onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", "inactive");
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onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active",
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"inactive");
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onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT);
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onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT);
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onoff("User Definable Features (UDF) support", rval, PCI_STATUS_UDF_SUPPORT);
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onoff("Fast back-to-back capable", rval, PCI_STATUS_BACKTOBACK_SUPPORT);
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onoff("User Definable Features (UDF) support", rval,
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PCI_STATUS_UDF_SUPPORT);
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onoff("Fast back-to-back capable", rval,
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PCI_STATUS_BACKTOBACK_SUPPORT);
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onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR);
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printf(" DEVSEL timing: ");
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@ -533,8 +543,10 @@ pci_conf_print_common(
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}
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printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25);
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onoff("Slave signaled Target Abort", rval, PCI_STATUS_TARGET_TARGET_ABORT);
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onoff("Master received Target Abort", rval, PCI_STATUS_MASTER_TARGET_ABORT);
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onoff("Slave signaled Target Abort", rval,
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PCI_STATUS_TARGET_TARGET_ABORT);
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onoff("Master received Target Abort", rval,
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PCI_STATUS_MASTER_TARGET_ABORT);
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onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT);
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onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR);
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onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT);
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@ -557,7 +569,8 @@ pci_conf_print_common(
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printf(" Subclass Name: %s (0x%02x)\n",
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subclassp->name, PCI_SUBCLASS(rval));
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else
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printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
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printf(" Subclass ID: 0x%02x\n",
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PCI_SUBCLASS(rval));
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} else {
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printf(" Class ID: 0x%02x\n", PCI_CLASS(rval));
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printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval));
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@ -744,73 +757,120 @@ pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast)
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printf("\n");
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}
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static void
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pci_conf_print_type0(
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#ifdef _KERNEL
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pci_chipset_tag_t pc, pcitag_t tag,
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#endif
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const pcireg_t *regs
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#ifdef _KERNEL
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, int sizebars
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#endif
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)
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static const char *
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pci_conf_print_pcipm_cap_aux(uint16_t caps)
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{
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int off, width;
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pcireg_t rval;
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for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) {
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#ifdef _KERNEL
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width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
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#else
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width = pci_conf_print_bar(regs, off, NULL);
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#endif
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switch ((caps >> 6) & 7) {
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case 0: return "self-powered";
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case 1: return "55 mA";
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case 2: return "100 mA";
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case 3: return "160 mA";
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case 4: return "220 mA";
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case 5: return "270 mA";
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case 6: return "320 mA";
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case 7:
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default: return "375 mA";
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}
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printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]);
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rval = regs[o2i(PCI_SUBSYS_ID_REG)];
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printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
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printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
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/* XXX */
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printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]);
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if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
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printf(" Capability list pointer: 0x%02x\n",
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PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
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else
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printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
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printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]);
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rval = regs[o2i(PCI_INTERRUPT_REG)];
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printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff);
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printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff);
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printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
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switch (PCI_INTERRUPT_PIN(rval)) {
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case PCI_INTERRUPT_PIN_NONE:
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printf("(none)");
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break;
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case PCI_INTERRUPT_PIN_A:
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printf("(pin A)");
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break;
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case PCI_INTERRUPT_PIN_B:
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printf("(pin B)");
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break;
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case PCI_INTERRUPT_PIN_C:
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printf("(pin C)");
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break;
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case PCI_INTERRUPT_PIN_D:
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printf("(pin D)");
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break;
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default:
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printf("(? ? ?)");
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break;
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}
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printf("\n");
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printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
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}
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static const char *
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pci_conf_print_pcipm_cap_pmrev(uint8_t val)
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{
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static const char unk[] = "unknown";
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static const char *pmrev[8] = {
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unk, "1.0", "1.1", "1.2", unk, unk, unk, unk
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};
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if (val > 7)
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return unk;
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return pmrev[val];
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}
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static void
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pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
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{
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uint16_t caps, pmcsr;
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pcireg_t reg;
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caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT;
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reg = regs[o2i(capoff + PCI_PMCSR)];
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pmcsr = reg & 0xffff;
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printf("\n PCI Power Management Capabilities Register\n");
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printf(" Capabilities register: 0x%04x\n", caps);
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printf(" Version: %s\n",
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pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK));
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onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK);
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onoff("Device specific initialization", caps, PCI_PMCR_DSI);
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printf(" 3.3V auxiliary current: %s\n",
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pci_conf_print_pcipm_cap_aux(caps));
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onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP);
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onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP);
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printf(" PME# support: 0x%02x\n", caps >> 11);
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printf(" Control/status register: 0x%04x\n", pmcsr);
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printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK);
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onoff("PCI Express reserved", (pmcsr >> 2), 1);
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onoff("No soft reset", (pmcsr >> 3), 1);
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printf(" PME# assertion: %sabled\n",
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(pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis");
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onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
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printf(" Bridge Support Extensions register: 0x%02x\n",
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(reg >> 16) & 0xff);
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onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT);
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onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN);
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printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff);
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}
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/* XXX pci_conf_print_vpd_cap */
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/* XXX pci_conf_print_slotid_cap */
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static void
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pci_conf_print_msi_cap(const pcireg_t *regs, int capoff)
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{
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uint32_t ctl, mmc, mme;
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regs += o2i(capoff);
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ctl = *regs++;
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mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK);
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mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK);
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printf("\n PCI Message Signaled Interrupt\n");
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printf(" Message Control register: 0x%04x\n", ctl >> 16);
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onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE);
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printf(" Multiple Message Capable: %s (%d vector%s)\n",
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mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : "");
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printf(" Multiple Message Enabled: %s (%d vector%s)\n",
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mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : "");
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onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR);
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onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK);
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printf(" Message Address %sregister: 0x%08x\n",
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ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++);
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if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
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printf(" Message Address %sregister: 0x%08x\n",
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"(upper) ", *regs++);
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}
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printf(" Message Data register: 0x%08x\n", *regs++);
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if (ctl & PCI_MSI_CTL_PERVEC_MASK) {
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printf(" Vector Mask register: 0x%08x\n", *regs++);
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printf(" Vector Pending register: 0x%08x\n", *regs++);
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}
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}
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/* XXX pci_conf_print_cpci_hostwap_cap */
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/* XXX pci_conf_print_pcix_cap */
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/* XXX pci_conf_print_ldt_cap */
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/* XXX pci_conf_print_vendspec_cap */
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/* XXX pci_conf_print_debugport_cap */
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/* XXX pci_conf_print_cpci_rsrcctl_cap */
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/* XXX pci_conf_print_hotplug_cap */
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/* XXX pci_conf_print_subvendor_cap */
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/* XXX pci_conf_print_agp8_cap */
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/* XXX pci_conf_print_secure_cap */
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static void
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pci_print_pcie_L0s_latency(uint32_t val)
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{
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@ -1373,104 +1433,10 @@ pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
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/* Slot Status 2 */
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}
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static const char *
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pci_conf_print_pcipm_cap_aux(uint16_t caps)
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{
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switch ((caps >> 6) & 7) {
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case 0: return "self-powered";
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case 1: return "55 mA";
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case 2: return "100 mA";
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case 3: return "160 mA";
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case 4: return "220 mA";
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case 5: return "270 mA";
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case 6: return "320 mA";
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case 7:
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default: return "375 mA";
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}
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}
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/* XXX pci_conf_print_msix_cap */
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/* XXX pci_conf_print_sata_cap */
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/* XXX pci_conf_print_pciaf_cap */
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static const char *
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pci_conf_print_pcipm_cap_pmrev(uint8_t val)
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{
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static const char unk[] = "unknown";
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static const char *pmrev[8] = {
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unk, "1.0", "1.1", "1.2", unk, unk, unk, unk
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};
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if (val > 7)
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return unk;
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return pmrev[val];
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}
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static void
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pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
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{
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uint16_t caps, pmcsr;
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pcireg_t reg;
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caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT;
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reg = regs[o2i(capoff + PCI_PMCSR)];
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pmcsr = reg & 0xffff;
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printf("\n PCI Power Management Capabilities Register\n");
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printf(" Capabilities register: 0x%04x\n", caps);
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printf(" Version: %s\n",
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pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK));
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onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK);
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onoff("Device specific initialization", caps, PCI_PMCR_DSI);
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printf(" 3.3V auxiliary current: %s\n",
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pci_conf_print_pcipm_cap_aux(caps));
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onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP);
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onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP);
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printf(" PME# support: 0x%02x\n", caps >> 11);
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printf(" Control/status register: 0x%04x\n", pmcsr);
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printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK);
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onoff("PCI Express reserved", (pmcsr >> 2), 1);
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onoff("No soft reset", (pmcsr >> 3), 1);
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printf(" PME# assertion: %sabled\n",
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(pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis");
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onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
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printf(" Bridge Support Extensions register: 0x%02x\n",
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(reg >> 16) & 0xff);
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onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT);
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onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN);
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printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff);
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}
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static void
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pci_conf_print_msi_cap(const pcireg_t *regs, int capoff)
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{
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uint32_t ctl, mmc, mme;
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regs += o2i(capoff);
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ctl = *regs++;
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mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK);
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mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK);
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printf("\n PCI Message Signaled Interrupt\n");
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printf(" Message Control register: 0x%04x\n", ctl >> 16);
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onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE);
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printf(" Multiple Message Capable: %s (%d vector%s)\n",
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mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : "");
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printf(" Multiple Message Enabled: %s (%d vector%s)\n",
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mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : "");
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onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR);
|
||||
onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK);
|
||||
printf(" Message Address %sregister: 0x%08x\n",
|
||||
ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++);
|
||||
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
|
||||
printf(" Message Address %sregister: 0x%08x\n",
|
||||
"(upper) ", *regs++);
|
||||
}
|
||||
printf(" Message Data register: 0x%08x\n", *regs++);
|
||||
if (ctl & PCI_MSI_CTL_PERVEC_MASK) {
|
||||
printf(" Vector Mask register: 0x%08x\n", *regs++);
|
||||
printf(" Vector Pending register: 0x%08x\n", *regs++);
|
||||
}
|
||||
}
|
||||
static void
|
||||
pci_conf_print_caplist(
|
||||
#ifdef _KERNEL
|
||||
@ -1561,12 +1527,28 @@ pci_conf_print_caplist(
|
||||
}
|
||||
printf(")\n");
|
||||
}
|
||||
if (msi_off != -1)
|
||||
pci_conf_print_msi_cap(regs, msi_off);
|
||||
if (pcipm_off != -1)
|
||||
pci_conf_print_pcipm_cap(regs, pcipm_off);
|
||||
/* XXX AGP */
|
||||
/* XXX VPD */
|
||||
/* XXX SLOTID */
|
||||
if (msi_off != -1)
|
||||
pci_conf_print_msi_cap(regs, msi_off);
|
||||
/* XXX CPCI_HOTSWAP */
|
||||
/* XXX PCIX */
|
||||
/* XXX LDT */
|
||||
/* XXX VENDSPEC */
|
||||
/* XXX DEBUGPORT */
|
||||
/* XXX CPCI_RSRCCTL */
|
||||
/* XXX HOTPLUG */
|
||||
/* XXX SUBVENDOR */
|
||||
/* XXX AGP8 */
|
||||
/* XXX SECURE */
|
||||
if (pcie_off != -1)
|
||||
pci_conf_print_pcie_cap(regs, pcie_off);
|
||||
/* XXX MSIX */
|
||||
/* XXX SATA */
|
||||
/* XXX PCIAF */
|
||||
}
|
||||
|
||||
/* Print the Secondary Status Register. */
|
||||
@ -1606,6 +1588,73 @@ pci_conf_print_ssr(pcireg_t rval)
|
||||
onoff("Detected parity error", rval, __BIT(15));
|
||||
}
|
||||
|
||||
static void
|
||||
pci_conf_print_type0(
|
||||
#ifdef _KERNEL
|
||||
pci_chipset_tag_t pc, pcitag_t tag,
|
||||
#endif
|
||||
const pcireg_t *regs
|
||||
#ifdef _KERNEL
|
||||
, int sizebars
|
||||
#endif
|
||||
)
|
||||
{
|
||||
int off, width;
|
||||
pcireg_t rval;
|
||||
|
||||
for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) {
|
||||
#ifdef _KERNEL
|
||||
width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars);
|
||||
#else
|
||||
width = pci_conf_print_bar(regs, off, NULL);
|
||||
#endif
|
||||
}
|
||||
|
||||
printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]);
|
||||
|
||||
rval = regs[o2i(PCI_SUBSYS_ID_REG)];
|
||||
printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval));
|
||||
printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval));
|
||||
|
||||
/* XXX */
|
||||
printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]);
|
||||
|
||||
if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)
|
||||
printf(" Capability list pointer: 0x%02x\n",
|
||||
PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]));
|
||||
else
|
||||
printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
|
||||
|
||||
printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]);
|
||||
|
||||
rval = regs[o2i(PCI_INTERRUPT_REG)];
|
||||
printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff);
|
||||
printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff);
|
||||
printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval));
|
||||
switch (PCI_INTERRUPT_PIN(rval)) {
|
||||
case PCI_INTERRUPT_PIN_NONE:
|
||||
printf("(none)");
|
||||
break;
|
||||
case PCI_INTERRUPT_PIN_A:
|
||||
printf("(pin A)");
|
||||
break;
|
||||
case PCI_INTERRUPT_PIN_B:
|
||||
printf("(pin B)");
|
||||
break;
|
||||
case PCI_INTERRUPT_PIN_C:
|
||||
printf("(pin C)");
|
||||
break;
|
||||
case PCI_INTERRUPT_PIN_D:
|
||||
printf("(pin D)");
|
||||
break;
|
||||
default:
|
||||
printf("(? ? ?)");
|
||||
break;
|
||||
}
|
||||
printf("\n");
|
||||
printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval));
|
||||
}
|
||||
|
||||
static void
|
||||
pci_conf_print_type1(
|
||||
#ifdef _KERNEL
|
||||
@ -1727,8 +1776,8 @@ pci_conf_print_type1(
|
||||
}
|
||||
if (pbase < plimit) {
|
||||
if (use_upper == 1)
|
||||
printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 "\n",
|
||||
pbase, plimit);
|
||||
printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64
|
||||
"\n", pbase, plimit);
|
||||
else
|
||||
printf(" range: 0x%08x-0x%08x\n",
|
||||
(uint32_t)pbase, (uint32_t)plimit);
|
||||
@ -1878,7 +1927,8 @@ pci_conf_print_type2(
|
||||
onoff("VGA enable", rval, __BIT(3));
|
||||
onoff("Master abort mode", rval, __BIT(5));
|
||||
onoff("Secondary (CardBus) bus reset", rval, __BIT(6));
|
||||
onoff("Functional interrupts routed by ExCA registers", rval, __BIT(7));
|
||||
onoff("Functional interrupts routed by ExCA registers", rval,
|
||||
__BIT(7));
|
||||
onoff("Memory window 0 prefetchable", rval, __BIT(8));
|
||||
onoff("Memory window 1 prefetchable", rval, __BIT(9));
|
||||
onoff("Write posting enable", rval, __BIT(10));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user