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408 Commits

Author SHA1 Message Date
lazymio
ef6f8a2427
Fix x86 CPUID 2021-12-22 23:39:41 +01:00
lazymio
7bb0abb977
Format 2021-12-22 20:37:15 +01:00
lazymio
7bb756249a
Better design of cpuid instruction hook 2021-12-22 20:36:56 +01:00
Quentin DUCASSE
033e79abac Added cache flush after code patching in unit tests for arm64 and riscv 2021-12-17 14:55:08 +01:00
Dimitris Glynos
63a445cbba
fxsave / fxsave64 should store the floating point instruction pointer (fpip) (#1467) 
* fxsave / fxsave64 should store the floating point instruction pointer (fpip)
- fxsave / fxsave64 happen to be used as GetPC code in exploits

* unit tests for the storage of FPIP in fxsave (x86) and fxsave64 (x64)
 2021-12-13 08:40:32 +08:00
Quentin DUCASSE
549274f44c Code patching tests for riscv and arm64 2021-12-10 15:27:54 +01:00
Nguyen Anh Quynh
b042a6a01d add missing files 2021-12-06 04:28:13 +08:00
lazymio
8a0ca8715e
Fix SR read/write and a test 2021-12-04 23:22:28 +01:00
lazymio
221cde18df
Write CPSR as it is initiated from instructions to allow regs switch 2021-11-24 17:10:51 +01:00
lazymio
78e0ddbc4d
Fix mmio unmap 2021-11-24 00:18:19 +01:00
lazymio
4ed1c4cff9
Fix test name typo 2021-11-23 23:24:53 +01:00
Sven Bartscher
3e2580ef9e Add test case for #1497 2021-11-23 22:47:20 +01:00
lazymio
e11cc16e54
Implement high-resolution clock for mingw64 in test_ctl 2021-11-23 14:15:18 +01:00
lazymio
ccfb66611f
Move test to test_mem 2021-11-23 00:41:49 +01:00
Sven Bartscher
b35dbb90b2 Add test case for #1495 2021-11-22 18:48:16 +01:00
lazymio
907ec5095d
Fix a stackoverflow in tests 2021-11-21 19:28:45 +01:00
lazymio
fc467edbc6
Fix 32bit target getting wrong offset for mmio 2021-11-16 22:40:57 +01:00
lazymio
247ffbe0e8
Support nested uc_emu_start calls 2021-11-16 21:07:03 +01:00
lazymio
640251e1aa
Leave out size parameter in callback 2021-11-09 00:21:34 +01:00
lazymio
35017a614f
Slightly change UC_CTL_TB_REMOVE_CACHE 2021-11-08 22:09:33 +01:00
lazymio
e836b62e01
Minor fix for uc_ctl 2021-11-08 20:40:02 +01:00
lazymio
2f61592ff9
Fix uc_mem_protect 2021-11-07 20:37:58 +01:00
lazymio
c6fdbb3735
Add RISCV CSR registers 2021-11-07 20:36:04 +01:00
lazymio
01d7e454b7
Fix typo 2021-11-04 20:59:07 +01:00
lazymio
3aa2788586
Format 2021-11-04 18:39:52 +01:00
lazymio
dfbffa44ec
Support changing cpu model for ARM 2021-11-04 18:37:10 +01:00
lazymio
3e4b4af7d3
Support change page size 2021-11-04 17:03:30 +01:00
lazymio
67e2386da6
Add test and close #1477 2021-11-03 21:40:13 +01:00
lazymio
1a82248292
Add test for #992 2021-11-03 21:17:57 +01:00
lazymio
6b5529fcb7
Merge pull request #1458 from bet4it/patch 
Port some patches from Unicorn1 to Unicorn2
 2021-11-03 20:59:42 +01:00
lazymio
9818840f4e
Add tests for UC_HOOK_TCG_OPCODE 2021-11-03 20:56:45 +01:00
lazymio
58edb2abe7
Format 2021-11-03 13:28:12 +01:00
lazymio
09aa0f944f
Merge QDucasse:riscv_extension_d 
Fix and close #1469

Fix test for riscv float points

Fix the riscv cpu config we left out
 2021-11-03 13:20:46 +01:00
lazymio
eb75d459f0
Add a regression test for invalidating empty TB and have a better solution 2021-11-03 01:07:06 +01:00
Bet4
aaf340d9e4 Merge branch 'dev' into patch 2021-11-02 18:36:22 +08:00
lazymio
b7e82d460c
Expose more TB related stuff 2021-11-01 22:11:43 +01:00
lazymio
14e175394b
Fix Win32 time function for test_ctl 2021-11-01 19:43:30 +01:00
lazymio
9704618595
Fix test for Android due to clock() not working 2021-11-01 15:33:36 +01:00
lazymio
cee44b0464
Add tests and samples to show how to control TB cache 2021-11-01 14:46:01 +01:00
lazymio
fb45b287ba
Add multiple exits mechanism and tests&samples 2021-11-01 14:00:43 +01:00
lazymio
147cb62240
Add uc_close 2021-11-01 10:23:47 +01:00
lazymio
3dd2e0f95d
Basic implementation of uc_ctl 2021-11-01 00:39:36 +01:00
lazymio
84abf1d3a4
A stronger test and handle addr_end = 0 2021-10-31 21:01:55 +01:00
lazymio
4bcf1c4a7c
Flush TB at exit with a better approach instead of flushing tlb in uc1 2021-10-31 19:43:56 +01:00
lazymio
8e6f7e4fba
Add a regression test 2021-10-31 15:56:58 +01:00
lazymio
e62b0ef255
Add clang-format and format code to qemu code style 2021-10-29 12:44:49 +02:00
lazymio
9131856506
More tests 2021-10-26 11:32:57 +02:00
Aurimas Blažulionis
160045a910
Binary search mapped blocks 2021-10-20 20:49:55 +01:00
mio
91451aa2f5
Add a new unit test file 2021-10-20 21:27:22 +02:00
mio
30f0e24407
Merge remote-tracking branch 'qducasse/riscv_pc_update' into dev 2021-10-19 23:08:41 +02:00
Quentin DUCASSE
5fd90ca1ef Added 3 steps unit test 2021-10-19 17:20:10 +02:00
Quentin DUCASSE
47f986fc93 Unit test POC for RISCV issue 2021-10-19 17:12:52 +02:00
Bet4
c400924fe1
Merge branch 'dev' into patch 2021-10-17 18:18:09 +08:00
mio
6d0d0897f8
Fix Rust build and CI. 
Add a test for ppc and fix ppc on windows.
 2021-10-17 02:11:38 +02:00
insane-shane
47ecfc1b2c Handle exceptions raised in Python hook functions (#1387) 2021-10-12 08:35:52 +08:00
mio
9d8a309fbf
Allow user to instrument cpuid instruction 2021-10-05 17:15:49 +02:00
mio
bccc7f2fb7
Remove NULL tcg arg and add a test for sysenter 2021-10-04 18:50:42 +02:00
mio
2d043d387d
Change mips model to add DSP 2021-10-03 23:10:39 +02:00
Nguyen Anh Quynh
aaaea14214 import Unicorn2 2021-10-03 22:14:44 +08:00
insane-shane
4f9a6cfcf3
Handle exceptions raised in Python hook functions (#1387) 2021-04-26 00:35:56 +08:00
lazymio
b0f1e46f61
Fix fpip (#1385) 
* Revert partial #74

* Import fix from https://lists.nongnu.org/archive/html/qemu-devel/2021-04/msg02868.html

* Fix capstone usage
 2021-04-26 00:32:42 +08:00
h01G3r
a9025c58a4
fixes an issue with ARM APSR register handling: (#1317) 
- Q flag / GE flag were not included in APSR register (read/write)
  - UC_ARM_REG_APSR_NZCV register constant was ignored completely.
  - regression test added
 2020-08-20 23:24:04 +08:00
Nguyen Anh Quynh
ac68fd441d fix test_x86.c 2020-05-25 00:04:07 +08:00
Nguyen Anh Quynh
fbef45b18f remove UC_ERR_TIMEOUT, so timeout on uc_emu_start() is not considered error. added UC_QUERY_TIMEOUT to query exit reason 2020-05-24 23:54:45 +08:00
Catena cyber
216c348c35
Oss-fuzz ideal integration (#1262) 
* Fix watchpoint leak in ARM

* Builds fuzz targets with sanitizer support

* Builds fuzz targets with directory driver

* Adds script to dowlonad public corpus

* Adds CIfuzz

To checks Pull Requests with fuzzing

* Use static library for fuzz targets

* Less verbose logs for fuzz driver directory
 2020-05-21 16:15:12 +08:00
Chen Huitao
2c66acf4ee
fix #1246 (#1254) 
* fix finding python path which only has python3.

* fix #1246, arm host issue.

* skip assembler tests on non-x86 host.

* update macro of dummy value.

* fix MSVC macro.

* update dummy array value macro.

* restore to original qemu code.
 2020-05-18 19:57:44 +08:00
Chen Huitao
18a187b8f8
fix some oss-fuzz (#1255) 
* fix oss-fuzz 22107.

* fix oss-fuzz 22112.

* clean up build target.
 2020-05-12 01:27:47 +08:00
Dominik Maier
9fedbd96f4
fixed leaks in test cases (#1247) 2020-05-02 18:18:18 +08:00
David CARLIER
72f7598387 Tests, fixes on third platform. (#1168) 
MT linkage fix mainly.
 2019-12-29 00:18:40 +08:00
ζeh Matt
3a3bc0c22d Timeout error (#1173) 
* Implement timeout state and new error for such case

* Adjust test_i386_loop sample

* Adjust test_i386_loop test
 2019-12-29 00:16:54 +08:00
Daniel Deptford
bc572be472 Check for TLB invalidation after read callback(s). (#1122) 
* Adding regression test for issue where writing memory into a read only segment during a access callback fails.

* Check for TLB invalidation when calling read callbacks;  Writes to read-only memory by the callback cause a TLB flush which requires a re-read of the TLB.
 2019-08-22 17:54:24 +08:00
dmarxn
5bf6d77e4e Fixed the decoding of opcodes after getting vex2 using 0xc5 (#1064) 
* Fixed the decoding of opcodes after getting vex2 using 0xc5

* Added testcase for vex. Can and should be expanded

* Fixed warning of testcase for vex (parentheses for assignment)
 2019-02-25 21:14:20 +08:00
Catena cyber
12bcf3bea0 Fuzz builds ok (#1007) 
* Fuzzing M68K without abort

* UC_MODE_32 is not ok with sparc

use UC_MODE_SPARC32|UC_MODE_BIG_ENDIAN instead

* Temporary removing leaking on start targets

* Do not abort for m68K undef instructions
 2018-09-11 12:49:32 +08:00
Catena cyber
feb46abb4a Fuzz (#1000) 
* Integration with oss-fuzz

* Use CFLAGS even for linking

as for fuzzing with asan

* Do not abort on uc_emu_start error

* Redirect fuzz output somewhere else than stdout

* Use uc_open for every fuzz instance

* Avoids timeouts from infinite loops

Limiting the number of instructions

* Moving fuzz to tests directory
 2018-08-29 10:36:23 +08:00
toshiMSFT
0f14c47344 Makes SYSENTER hookable again on x86 (#996) 
Adds SYSENTER to the whitelist of supported hookable instructions in unicorn
as well as fixes up the existing sysenter_hook_x86 regression test which was
previously failing

Fixes unicorn-engine/unicorn#995
 2018-08-09 23:32:31 +08:00
Willi Ballenthin
d331b8f7d8 add 64-bit test demonstrating setting MSRs and FS/GS segments (#901) 
* add x86_64_msr.py test demonstrating setting MSRs and FS/GS segments

* x86_64_msr.py: remove references to hooks

* x86_64_msr.py: remove references to old global variable
 2017-09-29 04:26:23 +08:00
Jean-Baptiste Cayrou
b1995b4b8a Fix C syntax mistake in test_gdt_idt_x86.c (#867) 
Now 'make test' command works
 2017-08-07 10:31:10 +08:00
Nguyen Anh Quynh
de7bf524f3 tests: fix mem_fuzz.c - FIXME 2017-07-23 16:33:57 +08:00
Nguyen Anh Quynh
281177aa9d regress: an attempt to fix build error on mem_fuzz.c 2017-07-22 23:40:59 +08:00
Stephen
da21bd0589 Start moving examples in S files (#851) 
* Move assembly to S files

* more assembly files

* osx compilation change

* makefile mistake

* add objcopy from crosstool

* use gobjcopy on osx

* start cmocka install cleanup

* move wget to directory option

* move back to cd

* fix copy

* First cut

* free allocated memory

* bad idea

too much switching between python and c

* add debug

* cleanup bad size
 2017-06-25 10:14:22 +08:00
Stephen
7f116846c0 MSYS test (#852) 
* MSYS test

using new cmocka msys package

* Update .appveyor.yml

* temp package install

before real ones get uploaded to db

* Update .appveyor.yml

* Update .appveyor.yml

* Update .appveyor.yml

* Update Makefile

* Update test_x86_shl_enter_leave.c

* Update Makefile

* Update threaded_emu_start.c

* Update .appveyor.yml

* remove unused install
 2017-06-25 10:11:35 +08:00
Nguyen Anh Quynh
c01dcf0a14 fix merge conflicts 2017-03-10 21:04:33 +08:00
Nguyen Anh Quynh
70db329749 regress: ignore arm_enable_vfp 2017-02-26 10:50:18 +08:00
Nguyen Anh Quynh
a40e5aae09 regress: fix warning on compilation on eflags_noset.c. see #764 2017-02-25 11:20:26 +08:00
Nguyen Anh Quynh
b12ce92468 regress: eflags_noset.c should only asm x86 code on x86 platform. fix #764 2017-02-25 01:14:47 +08:00
Nguyen Anh Quynh
6ea39f7d5a merge msvc with master 2017-02-24 10:39:36 +08:00
Parker Thompson
053ecd7bf4 Added ARM coproc registers (#684) 
* Added ARM coproc registers

* Added regression test for vfp
 2017-01-25 11:56:19 +08:00
xorstream
cbd0e6056c Fixed some conflicts 2017-01-23 11:35:00 +11:00
xorstream
724c765028 Merging with current msvc 2 2017-01-23 01:07:50 +11:00
Nguyen Anh Quynh
206819bd98 cleanup after msvc port 2017-01-22 21:27:17 +08:00
Nguyen Anh Quynh
f9f184e719 test: fix missng pthread functions 2017-01-21 22:29:07 +08:00
Nguyen Anh Quynh
de9083a532 test: fix missng pthread functions 2017-01-21 22:22:09 +08:00
xorstream
770c5616e2 Automated leading tab to spaces conversion. 2017-01-21 12:28:22 +11:00
xorstream
837d3787c0 Fix for read()/write() conflict with unistd.h in test_mem_map.c. 2017-01-21 01:39:49 +11:00
xorstream
fac6a66860 platform.h move #3 2017-01-21 00:13:21 +11:00
xorstream
1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
Elton G
47150b6df3 reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) 
* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton

* Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30)
Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write

* Fixed WRITE_DWORD macro

reg_write would zero out the high order bits when writing to 32 bit registers

e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
 2017-01-15 20:13:35 +08:00
Nguyen Anh Quynh
55f0292aa9 Merge branch 'master' of https://github.com/unicorn-engine/unicorn 2017-01-13 20:13:31 +08:00
Nguyen Anh Quynh
353dc99af6 regress: fix arm_fp_vfp_disabled.py 2017-01-13 20:13:20 +08:00
hedger
d2b7d13443 Fixed circular refs preventing Uc instances from being GC'd. Added a test case, requires objgraph module. 2017-01-11 18:23:21 +03:00