Slightly change UC_CTL_TB_REMOVE_CACHE
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6ec016327d
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35017a614f
@ -522,7 +522,7 @@ typedef enum uc_control_type {
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// Read: @args = (uint64_t, uc_tb*)
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UC_CTL_TB_REQUEST_CACHE,
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// Invalidate a tb cache at a specific address
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// Write: @args = (uint64_t)
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// Write: @args = (uint64_t, uint64_t)
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UC_CTL_TB_REMOVE_CACHE
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} uc_control_type;
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@ -594,8 +594,8 @@ See sample_ctl.c for a detailed example.
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uc_ctl(uc, UC_CTL_READ(UC_CTL_CPU_MODEL, 1), (model))
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#define uc_ctl_set_cpu_model(uc, model) \
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uc_ctl(uc, UC_CTL_WRITE(UC_CTL_CPU_MODEL, 1), (model))
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#define uc_ctl_remove_cache(uc, address) \
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uc_ctl(uc, UC_CTL_WRITE(UC_CTL_TB_REMOVE_CACHE, 1), (address))
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#define uc_ctl_remove_cache(uc, address, end) \
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uc_ctl(uc, UC_CTL_WRITE(UC_CTL_TB_REMOVE_CACHE, 2), (address), (end))
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#define uc_ctl_request_cache(uc, address, tb) \
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uc_ctl(uc, UC_CTL_READ_WRITE(UC_CTL_TB_REQUEST_CACHE, 2), (address), (tb))
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@ -258,7 +258,8 @@ static void test_uc_ctl_tb_cache()
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// Now we clear cache for all TBs.
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for (int i = 0; i < TB_COUNT; i++) {
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err = uc_ctl_remove_cache(uc, ADDRESS + i * TCG_MAX_INSNS);
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err = uc_ctl_remove_cache(uc, ADDRESS + i * TCG_MAX_INSNS,
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ADDRESS + i * TCG_MAX_INSNS + 1);
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if (err) {
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printf("Failed on uc_ctl() with error returned: %u\n", err);
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return;
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@ -144,7 +144,8 @@ static void test_uc_ctl_tb_cache()
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cached = time_emulation(uc, code_start, code_start + sizeof(code) - 1);
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for (int i = 0; i < TB_COUNT; i++) {
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OK(uc_ctl_remove_cache(uc, code_start + i * TCG_MAX_INSNS));
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OK(uc_ctl_remove_cache(uc, code_start + i * TCG_MAX_INSNS,
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code_start + i * TCG_MAX_INSNS + 1));
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}
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evicted = time_emulation(uc, code_start, code_start + sizeof(code) - 1);
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7
uc.c
7
uc.c
@ -2105,7 +2105,12 @@ uc_err uc_ctl(uc_engine *uc, uc_control_type control, ...)
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if (rw == UC_CTL_IO_WRITE) {
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uint64_t addr = va_arg(args, uint64_t);
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uc->uc_invalidate_tb(uc, addr, 1);
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uint64_t end = va_arg(args, uint64_t);
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if (end <= addr) {
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err = UC_ERR_ARG;
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} else {
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uc->uc_invalidate_tb(uc, addr, end - addr);
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}
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} else {
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err = UC_ERR_ARG;
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}
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