Add test and close #1477
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@ -380,6 +380,10 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
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// Unicorn: Imported from https://github.com/unicorn-engine/unicorn/pull/1098
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CPUMIPSState *env = &(MIPS_CPU(cpu)->env);
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env->active_tc.PC = uc->next_pc;
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#endif
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#if defined(TARGET_RISCV)
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CPURISCVState *env = &(RISCV_CPU(uc->cpu)->env);
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env->pc += 4;
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#endif
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// Unicorn: call registered interrupt callbacks
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catched = false;
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@ -341,6 +341,32 @@ static void test_riscv64_fp_move_to_int(void)
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uc_close(uc);
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}
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static void test_riscv64_ecall_cb(uc_engine *uc, uint32_t intno, void *data)
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{
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uc_emu_stop(uc);
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return;
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}
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static void test_riscv64_ecall()
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{
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uc_engine *uc;
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char code[] = "\x73\x00\x00\x00"; // ecall
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uint64_t r_pc;
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uc_hook h;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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OK(uc_hook_add(uc, &h, UC_HOOK_INTR, test_riscv64_ecall_cb, NULL, 1, 0));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
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TEST_CHECK(r_pc == code_start + 4);
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OK(uc_close(uc));
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}
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TEST_LIST = {{"test_riscv32_nop", test_riscv32_nop},
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{"test_riscv64_nop", test_riscv64_nop},
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{"test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update},
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@ -351,4 +377,5 @@ TEST_LIST = {{"test_riscv32_nop", test_riscv32_nop},
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{"test_riscv64_fp_move", test_riscv64_fp_move},
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{"test_riscv64_fp_move_from_int", test_riscv64_fp_move_from_int},
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{"test_riscv64_fp_move_to_int", test_riscv64_fp_move_to_int},
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{"test_riscv64_ecall", test_riscv64_ecall},
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{NULL, NULL}};
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