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Change mips model to add DSP

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This commit is contained in:
mio 2021-10-03 23:10:39 +02:00
parent 0a7223996d
commit 2d043d387d
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GPG Key ID: DFF27E34A47CB873
4 changed files with 46 additions and 1 deletions
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1
include/unicorn/mips.h
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@ -177,6 +177,7 @@ typedef enum UC_MIPS_REG {
UC_MIPS_REG_CP0_CONFIG3,
UC_MIPS_REG_CP0_USERLOCAL,
UC_MIPS_REG_CP0_STATUS,
UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers

3
qemu/target/mips/cpu.c
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@ -162,7 +162,8 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc, const char *cpu_model)
#ifdef TARGET_MIPS64
cpu_model = "R4000";
#else
cpu_model = "24Kf";
// Add UC_MODE_ flag to select model?
cpu_model = "74Kf";
#endif
}

11
qemu/target/mips/unicorn.c
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@ -7,6 +7,7 @@
#include "unicorn_common.h"
#include "uc_priv.h"
#include "unicorn.h"
#include "internal.h"
#ifdef TARGET_MIPS64
typedef uint64_t mipsreg_t;
@ -82,6 +83,9 @@ static void reg_read(CPUMIPSState *env, unsigned int regid, void *value)
case UC_MIPS_REG_CP0_CONFIG3:
*(mipsreg_t *)value = env->CP0_Config3;
break;
case UC_MIPS_REG_CP0_STATUS:
*(mipsreg_t *)value = env->CP0_Status;
break;
case UC_MIPS_REG_CP0_USERLOCAL:
*(mipsreg_t *)value = env->active_tc.CP0_UserLocal;
break;
@ -104,6 +108,13 @@ static void reg_write(CPUMIPSState *env, unsigned int regid, const void *value)
case UC_MIPS_REG_CP0_CONFIG3:
env->CP0_Config3 = *(mipsreg_t *)value;
break;
case UC_MIPS_REG_CP0_STATUS:
// TODO: ALL CP0 REGS
// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00090-2B-MIPS32PRA-AFP-06.02.pdf
// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00582-2B-microMIPS32-AFP-05.04.pdf
env->CP0_Status = *(mipsreg_t *)value;
compute_hflags(env);
break;
case UC_MIPS_REG_CP0_USERLOCAL:
env->active_tc.CP0_UserLocal = *(mipsreg_t *)value;
break;

32
tests/unit/test_mips.c
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@ -81,10 +81,42 @@ static void test_mips_stop_at_delay_slot() {
OK(uc_close(uc));
}
static void test_mips_lwx_exception_issue_1314() {
uc_engine* uc;
char code[] = "\x0a\xc8\x79\x7e"; // lwx $t9, $t9($s3)
int reg;
uc_common_setup(&uc, UC_ARCH_MIPS, UC_MODE_32 | UC_MODE_LITTLE_ENDIAN, code, sizeof(code) - 1);
OK(uc_mem_map(uc, 0x10000, 0x4000, UC_PROT_ALL));
// Enable DSP
// https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00090-2B-MIPS32PRA-AFP-06.02.pdf
OK(uc_reg_read(uc, UC_MIPS_REG_CP0_STATUS, &reg));
reg |= (1 << 24);
OK(uc_reg_write(uc, UC_MIPS_REG_CP0_STATUS, &reg));
reg = 0;
OK(uc_reg_write(uc, UC_MIPS_REG_1, &reg));
OK(uc_reg_write(uc, UC_MIPS_REG_T9, &reg));
reg = 0xdeadbeef;
OK(uc_mem_write(uc, 0x10000, &reg, 4));
reg = 0x10000;
OK(uc_reg_write(uc, UC_MIPS_REG_S3, &reg));
OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
OK(uc_reg_read(uc, UC_MIPS_REG_T9, &reg));
TEST_CHECK(reg == 0xdeadbeef);
OK(uc_close(uc));
}
TEST_LIST = {
{ "test_mips_stop_at_branch", test_mips_stop_at_branch },
{ "test_mips_stop_at_delay_slot", test_mips_stop_at_delay_slot},
{ "test_mips_el_ori", test_mips_el_ori},
{ "test_mips_eb_ori", test_mips_eb_ori},
{ "test_mips_lwx_exception_issue_1314", test_mips_lwx_exception_issue_1314},
{ NULL, NULL }
};