reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716)
* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton * Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30) Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write * Fixed WRITE_DWORD macro reg_write would zero out the high order bits when writing to 32 bit registers e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
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@ -27,7 +27,7 @@
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#define READ_WORD(x) (x & 0xffff)
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#define READ_BYTE_H(x) ((x & 0xffff) >> 8)
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#define READ_BYTE_L(x) (x & 0xff)
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#define WRITE_DWORD(x, w) (x = (x & ~0xffffffff) | (w & 0xffffffff))
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#define WRITE_DWORD(x, w) (x = (x & ~0xffffffffLL) | (w & 0xffffffff))
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#define WRITE_WORD(x, w) (x = (x & ~0xffff) | (w & 0xffff))
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#define WRITE_BYTE_H(x, b) (x = (x & ~0xff00) | ((b & 0xff) << 8))
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#define WRITE_BYTE_L(x, b) (x = (x & ~0xff) | (b & 0xff))
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@ -50,9 +50,11 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28)
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if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28) {
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*(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0];
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else {
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} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
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*(int32_t *)value = READ_DWORD(ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_W0]);
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} else {
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switch(regid) {
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default: break;
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case UC_ARM64_REG_X29:
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@ -82,9 +84,11 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28)
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if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28) {
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ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(uint64_t *)value;
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else {
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} else if (regid >= UC_ARM64_REG_W0 && regid <= UC_ARM64_REG_W30) {
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WRITE_DWORD(ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_W0], *(uint32_t *)value);
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} else {
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switch(regid) {
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default: break;
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case UC_ARM64_REG_X29:
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@ -0,0 +1,30 @@
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#!/usr/bin/python
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from unicorn import *
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from unicorn.arm64_const import *
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from unicorn.x86_const import *
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import regress
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class Arm64RegReadWriteW0ThroughW30(regress.RegressTest):
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"""
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Testing the functionality to read/write 32-bit registers in AArch64
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See issue #716
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"""
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def runTest(self):
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uc = Uc(UC_ARCH_ARM64, UC_MODE_ARM)
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uc.reg_write(UC_ARM64_REG_X0, 0x1234567890abcdef)
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self.assertEquals(uc.reg_read(UC_ARM64_REG_X0), 0x1234567890abcdef)
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self.assertEquals(uc.reg_read(UC_ARM64_REG_W0), 0x90abcdef)
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uc.reg_write(UC_ARM64_REG_X30, 0xa1b2c3d4e5f6a7b8)
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self.assertEquals(uc.reg_read(UC_ARM64_REG_W30), 0xe5f6a7b8)
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uc.reg_write(UC_ARM64_REG_W30, 0xaabbccdd)
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self.assertEquals(uc.reg_read(UC_ARM64_REG_X30), 0xa1b2c3d4aabbccdd)
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self.assertEquals(uc.reg_read(UC_ARM64_REG_W30), 0xaabbccdd)
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if __name__ == '__main__':
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regress.main()
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