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@ -217,130 +217,138 @@ static void test_riscv64_3steps_pc_update()
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OK(uc_close(uc));
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}
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static void test_riscv32_fp_move(void) {
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uc_engine *uc;
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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static void test_riscv32_fp_move(void)
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{
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uc_engine *uc;
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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uint32_t r_f1 = 0x1234;
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uint32_t r_f3 = 0x5678;
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uint32_t r_f1 = 0x1234;
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uint32_t r_f3 = 0x5678;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code, sizeof(code) - 1);
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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sizeof(code) - 1);
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// initialize machine registers
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uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1);
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uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3);
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// initialize machine registers
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uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1);
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uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3);
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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TEST_CHECK(r_f1 == 0x1234);
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TEST_CHECK(r_f3 == 0x1234);
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TEST_CHECK(r_f1 == 0x1234);
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TEST_CHECK(r_f3 == 0x1234);
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uc_close(uc);
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uc_close(uc);
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}
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static void test_riscv64_fp_move(void) {
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uc_engine *uc;
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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static void test_riscv64_fp_move(void)
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{
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uc_engine *uc;
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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uint64_t r_f1 = 0x12341234;
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uint64_t r_f3 = 0x56785678;
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uint64_t r_f1 = 0x12341234;
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uint64_t r_f3 = 0x56785678;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3));
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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TEST_CHECK(r_f1 == 0x12341234);
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TEST_CHECK(r_f3 == 0x12341234);
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TEST_CHECK(r_f1 == 0x12341234);
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TEST_CHECK(r_f3 == 0x12341234);
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uc_close(uc);
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uc_close(uc);
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}
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static void test_riscv64_fp_move_from_int(void) {
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uc_engine *uc;
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// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
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// https://five-embeddev.com/quickref/csrs.html
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// We have to enable mstatus.fs
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char code[] = "\xf3\x90\x01\x30\x53\x00\x0b\xf2"; // csrrw x2, mstatus, x3; fmvd.d.x ft0, s6
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static void test_riscv64_fp_move_from_int(void)
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{
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uc_engine *uc;
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// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
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// https://five-embeddev.com/quickref/csrs.html
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// We have to enable mstatus.fs
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char code[] = "\xf3\x90\x01\x30\x53\x00\x0b\xf2"; // csrrw x2, mstatus, x3;
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// fmvd.d.x ft0, s6
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uint64_t r_ft0 = 0x12341234;
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uint64_t r_s6 = 0x56785678;
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uint64_t r_x3 = 0x6000;
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uint64_t r_ft0 = 0x12341234;
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uint64_t r_s6 = 0x56785678;
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uint64_t r_x3 = 0x6000;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6));
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6));
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// mstatus.fs
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OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3));
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// mstatus.fs
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OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 2));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 2));
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OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6));
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OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6));
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TEST_CHECK(r_ft0 == 0x56785678);
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TEST_CHECK(r_s6 == 0x56785678);
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TEST_CHECK(r_ft0 == 0x56785678);
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TEST_CHECK(r_s6 == 0x56785678);
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uc_close(uc);
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uc_close(uc);
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}
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static void test_riscv64_fp_move_to_int(void) {
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uc_engine *uc;
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// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
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// https://five-embeddev.com/quickref/csrs.html
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// We have to enable mstatus.fs
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char code[] = "\xf3\x90\x01\x30\x53\x0b\x00\xe2"; // csrrw x2, mstatus, x3; fmv.x.d s6, ft0
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static void test_riscv64_fp_move_to_int(void)
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{
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uc_engine *uc;
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// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
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// https://five-embeddev.com/quickref/csrs.html
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// We have to enable mstatus.fs
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char code[] = "\xf3\x90\x01\x30\x53\x0b\x00\xe2"; // csrrw x2, mstatus, x3;
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// fmv.x.d s6, ft0
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uint64_t r_ft0 = 0x12341234;
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uint64_t r_s6 = 0x56785678;
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uint64_t r_x3 = 0x6000;
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uint64_t r_ft0 = 0x12341234;
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uint64_t r_s6 = 0x56785678;
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uint64_t r_x3 = 0x6000;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6));
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// mstatus.fs
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OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3));
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 2));
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// mstatus.fs
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OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3));
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OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 2));
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TEST_CHECK(r_ft0 == 0x12341234);
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TEST_CHECK(r_s6 == 0x12341234);
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OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6));
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uc_close(uc);
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TEST_CHECK(r_ft0 == 0x12341234);
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TEST_CHECK(r_s6 == 0x12341234);
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uc_close(uc);
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}
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TEST_LIST = {
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{ "test_riscv32_nop", test_riscv32_nop },
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{ "test_riscv64_nop", test_riscv64_nop },
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{ "test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update },
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{ "test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update },
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{ "test_riscv32_until_pc_update", test_riscv32_until_pc_update },
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{ "test_riscv64_until_pc_update", test_riscv64_until_pc_update },
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{ "test_riscv32_fp_move", test_riscv32_fp_move },
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{ "test_riscv64_fp_move", test_riscv64_fp_move },
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{ "test_riscv64_fp_move_from_int", test_riscv64_fp_move_from_int },
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{ "test_riscv64_fp_move_to_int", test_riscv64_fp_move_to_int },
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{ NULL, NULL }
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};
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TEST_LIST = {{"test_riscv32_nop", test_riscv32_nop},
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{"test_riscv64_nop", test_riscv64_nop},
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{"test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update},
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{"test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update},
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{"test_riscv32_until_pc_update", test_riscv32_until_pc_update},
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{"test_riscv64_until_pc_update", test_riscv64_until_pc_update},
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{"test_riscv32_fp_move", test_riscv32_fp_move},
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{"test_riscv64_fp_move", test_riscv64_fp_move},
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{"test_riscv64_fp_move_from_int", test_riscv64_fp_move_from_int},
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{"test_riscv64_fp_move_to_int", test_riscv64_fp_move_to_int},
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{NULL, NULL}};
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