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qemu/target/riscv/insn32.decode

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target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:41 +03:00
#
# RISC-V translation routines for the RVXI Base Integer Instruction Set.
#
# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2 or later, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
target/riscv: Convert RV32F insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:51 +03:00
%rs3 27:5
target/riscv: Convert RVXI branch insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:42 +03:00
%rs2 20:5
%rs1 15:5
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:41 +03:00
%rd 7:5
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:12 +03:00
%sh5 20:5
target/riscv: support for 128-bit shift instructions Handling shifts for 32, 64 and 128 operation length for RV128, following the general framework for handling various olens proposed by Richard. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:01:02 +03:00
%sh6 20:6
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:41 +03:00
target/riscv: reformat @sh format encoding for B-extension Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 19:06:02 +03:00
%sh7 20:7
target/riscv: Convert RVXI csr insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:47 +03:00
%csr 20:12
target/riscv: Convert RV32F insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:51 +03:00
%rm 12:3
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:54 +03:00
%nf 29:3 !function=ex_plus_1
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:45 +03:00
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:41 +03:00
# immediates:
target/riscv: Convert RVXI branch insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:42 +03:00
%imm_i 20:s12
target/riscv: Convert RV32I load/store insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:43 +03:00
%imm_s 25:s7 7:5
target/riscv: Convert RVXI branch insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:42 +03:00
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:41 +03:00
%imm_u 12:s20 !function=ex_shift_12
target/riscv: rvk: add support for zknd/zkne extension in RV32 - add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:02 +03:00
%imm_bs 30:2 !function=ex_shift_3
target/riscv: rvk: add support for zkne/zknd extension in RV64 - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:03 +03:00
%imm_rnum 20:4
target/riscv: Add Zvbb ISA extension support This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Co-authored-by: William Salmon <will.salmon@codethink.co.uk> Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> [max.chou@sifive.com: Fix imm mode of vror.vi] Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: William Salmon <will.salmon@codethink.co.uk> Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Exposed x-zvbb property] Message-ID: <20230711165917.2629866-9-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:07 +03:00
%imm_z6 26:1 15:5
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:41 +03:00
target/riscv: Convert RVXI branch insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:42 +03:00
# Argument sets:
target/riscv: Name the argument sets for all of insn32 formats Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-04-01 06:11:48 +03:00
&empty
target/riscv: Convert RVXI branch insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:42 +03:00
&b imm rs2 rs1
target/riscv: Move gen_arith_imm() decoding into trans_* functions gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:54:03 +03:00
&i imm rs1 rd
target/riscv: Name the argument sets for all of insn32 formats Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-04-01 06:11:48 +03:00
&j imm rd
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:54:04 +03:00
&r rd rs1 rs2
target/riscv: rvb: count leading/trailing zeros Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 19:06:03 +03:00
&r2 rd rs1
target/riscv: Tidy trans_rvh.c.inc Exit early if check_access fails. Split out do_hlv, do_hsv, do_hlvx subroutines. Use dest_gpr, get_gpr in the new subroutines. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-24-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-08-23 22:55:28 +03:00
&r2_s rs1 rs2
target/riscv: Name the argument sets for all of insn32 formats Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-04-01 06:11:48 +03:00
&s imm rs1 rs2
&u imm rd
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:45 +03:00
&shift shamt rs1 rd
target/riscv: Convert RV32A insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:49 +03:00
&atomic aq rl rs2 rs1 rd
target/riscv: vector single-width integer add and subtract Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-11-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:58 +03:00
&rmrr vm rd rs1 rs2
target/riscv: vector floating-point square-root instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-37-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:24 +03:00
&rmr vm rd rs2
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:54 +03:00
&r2nfvm vm rd rs1 nf
&rnfvm vm rd rs1 rs2 nf
target/riscv: rvk: add support for zknd/zkne extension in RV32 - add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:02 +03:00
&k_aes shamt rs2 rs1 rd
target/riscv: Convert RVXI branch insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:42 +03:00
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:41 +03:00
# Formats 32:
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:54:04 +03:00
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
target/riscv: Move gen_arith_imm() decoding into trans_* functions gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:54:03 +03:00
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
target/riscv: Convert RVXI branch insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:42 +03:00
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
target/riscv: Name the argument sets for all of insn32 formats Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-04-01 06:11:48 +03:00
@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
@u .................... ..... ....... &u imm=%imm_u %rd
@j .................... ..... ....... &j imm=%imm_j %rd
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:41 +03:00
target/riscv: reformat @sh format encoding for B-extension Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 19:06:02 +03:00
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
target/riscv: Convert RVXI csr insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:47 +03:00
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:45 +03:00
target/riscv: Convert RV32A insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:49 +03:00
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
target/riscv: Convert RV32F insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:51 +03:00
@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
target/riscv: rvb: count leading/trailing zeros Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 19:06:03 +03:00
@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
target/riscv: Add Zvkned ISA extension support This commit adds support for the Zvkned vector-crypto extension, which consists of the following instructions: * vaesef.[vv,vs] * vaesdf.[vv,vs] * vaesdm.[vv,vs] * vaesz.vs * vaesem.[vv,vs] * vaeskf1.vi * vaeskf2.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Co-authored-by: William Salmon <will.salmon@codethink.co.uk> [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: William Salmon <will.salmon@codethink.co.uk> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned property] [max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl egs checking by helper function] [max.chou@sifive.com: Replaced bswap32 calls in aes key expanding] Message-ID: <20230711165917.2629866-10-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:08 +03:00
@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:54 +03:00
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
target/riscv: vector floating-point square-root instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-37-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:24 +03:00
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
target/riscv: vector element index instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-55-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:42 +03:00
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:54 +03:00
@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
target/riscv: floating-point scalar move instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-58-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:45 +03:00
@r2rd ....... ..... ..... ... ..... ....... %rs2 %rd
target/riscv: vector single-width integer add and subtract Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-11-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:58 +03:00
@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
target/riscv: vector integer add-with-carry / subtract-with-borrow instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-13-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:00 +03:00
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
target/riscv: vector integer merge and move instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-24-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:11 +03:00
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
target/riscv: Add Zvbb ISA extension support This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Co-authored-by: William Salmon <will.salmon@codethink.co.uk> Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> [max.chou@sifive.com: Fix imm mode of vror.vi] Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: William Salmon <will.salmon@codethink.co.uk> Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Exposed x-zvbb property] Message-ID: <20230711165917.2629866-9-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:07 +03:00
@r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=%imm_z6 %rd
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-72-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:57 +03:00
@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
target/riscv: rvv-1.0: add vsetivli instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-73-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:58 +03:00
@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
target/riscv: Allow generating hlv/hlvx/hsv instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>
2020-08-12 22:13:19 +03:00
@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
target/riscv: Convert RV32F insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:51 +03:00
target/riscv: Add hfence instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-01 04:02:36 +03:00
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
target/riscv: Move the hfence instructions to the rvh decode Also correct the name of the VVMA instruction. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-04-04 00:05:01 +03:00
@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
target/riscv: Add hfence instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-01 04:02:36 +03:00
target/riscv: Convert RV priv insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:55 +03:00
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
target/riscv: rvk: add support for zknd/zkne extension in RV32 - add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:02 +03:00
@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
target/riscv: rvk: add support for zkne/zknd extension in RV64 - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:03 +03:00
@i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd
target/riscv: rvk: add support for zknd/zkne extension in RV32 - add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:02 +03:00
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:12 +03:00
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
target/riscv: Convert RV priv insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:55 +03:00
target/riscv: support for 128-bit shift instructions Handling shifts for 32, 64 and 128 operation length for RV128, following the general framework for handling various olens proposed by Richard. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:01:02 +03:00
# Formats 128:
@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
target/riscv: Convert RV priv insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:55 +03:00
# *** Privileged Instructions ***
target/riscv: Add hfence instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-01 04:02:36 +03:00
ecall 000000000000 00000 000 00000 1110011
ebreak 000000000001 00000 000 00000 1110011
uret 0000000 00010 00000 000 00000 1110011
sret 0001000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
target/riscv: Convert RV priv insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:55 +03:00
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:41 +03:00
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
auipc .................... ..... 0010111 @u
target/riscv: Convert RVXI branch insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:42 +03:00
jal .................... ..... 1101111 @j
jalr ............ ..... 000 ..... 1100111 @i
beq ....... ..... ..... 000 ..... 1100011 @b
bne ....... ..... ..... 001 ..... 1100011 @b
blt ....... ..... ..... 100 ..... 1100011 @b
bge ....... ..... ..... 101 ..... 1100011 @b
bltu ....... ..... ..... 110 ..... 1100011 @b
bgeu ....... ..... ..... 111 ..... 1100011 @b
target/riscv: Convert RV32I load/store insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:43 +03:00
lb ............ ..... 000 ..... 0000011 @i
lh ............ ..... 001 ..... 0000011 @i
lw ............ ..... 010 ..... 0000011 @i
lbu ............ ..... 100 ..... 0000011 @i
lhu ............ ..... 101 ..... 0000011 @i
sb ....... ..... ..... 000 ..... 0100011 @s
sh ....... ..... ..... 001 ..... 0100011 @s
sw ....... ..... ..... 010 ..... 0100011 @s
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:45 +03:00
addi ............ ..... 000 ..... 0010011 @i
slti ............ ..... 010 ..... 0010011 @i
sltiu ............ ..... 011 ..... 0010011 @i
xori ............ ..... 100 ..... 0010011 @i
target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder The cmo.prefetch instructions are nops for QEMU (no emulation of the memory hierarchy, no illegal instructions, no permission faults, no traps). Add a comment noting where they would be decoded in case cbo.prefetch instructions become relevant in the future. Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-24 16:25:36 +03:00
# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded.
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:45 +03:00
ori ............ ..... 110 ..... 0010011 @i
andi ............ ..... 111 ..... 0010011 @i
target/riscv: reformat @sh format encoding for B-extension Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 19:06:02 +03:00
slli 00000. ...... ..... 001 ..... 0010011 @sh
srli 00000. ...... ..... 101 ..... 0010011 @sh
srai 01000. ...... ..... 101 ..... 0010011 @sh
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:45 +03:00
add 0000000 ..... ..... 000 ..... 0110011 @r
sub 0100000 ..... ..... 000 ..... 0110011 @r
sll 0000000 ..... ..... 001 ..... 0110011 @r
slt 0000000 ..... ..... 010 ..... 0110011 @r
sltu 0000000 ..... ..... 011 ..... 0110011 @r
xor 0000000 ..... ..... 100 ..... 0110011 @r
srl 0000000 ..... ..... 101 ..... 0110011 @r
sra 0100000 ..... ..... 101 ..... 0110011 @r
or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
target/riscv: Add Zihintpause support Added support for RISC-V PAUSE instruction from Zihintpause extension, enabled by default. Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Dao Lu <daolu@rivosinc.com> Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-25 06:47:28 +03:00
{
pause 0000 0001 0000 00000 000 00000 0001111
fence ---- pred:4 succ:4 ----- 000 ----- 0001111
}
target/riscv: Convert RVXI fence insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:46 +03:00
fence_i ---- ---- ---- ----- 001 ----- 0001111
target/riscv: Convert RVXI csr insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:47 +03:00
csrrw ............ ..... 001 ..... 1110011 @csr
csrrs ............ ..... 010 ..... 1110011 @csr
csrrc ............ ..... 011 ..... 1110011 @csr
csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
target/riscv: Convert RVXM insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:48 +03:00
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:12 +03:00
# *** RV64I Base Instruction Set (in addition to RV32I) ***
lwu ............ ..... 110 ..... 0000011 @i
ld ............ ..... 011 ..... 0000011 @i
sd ....... ..... ..... 011 ..... 0100011 @s
addiw ............ ..... 000 ..... 0011011 @i
slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
addw 0000000 ..... ..... 000 ..... 0111011 @r
subw 0100000 ..... ..... 000 ..... 0111011 @r
sllw 0000000 ..... ..... 001 ..... 0111011 @r
srlw 0000000 ..... ..... 101 ..... 0111011 @r
sraw 0100000 ..... ..... 101 ..... 0111011 @r
target/riscv: accessors to registers upper part and 128-bit load/store Get function to retrieve the 64 top bits of a register, stored in the gprh field of the cpu state. Set function that writes the 128-bit value at once. The access to the gprh field can not be protected at compile time to make sure it is accessed only in the 128-bit version of the processor because we have no way to indicate that the misa_mxl_max field is const. The 128-bit ISA adds ldu, lq and sq. We provide support for these instructions. Note that (a) we compute only 64-bit addresses to actually access memory, cowardly utilizing the existing address translation mechanism of QEMU, and (b) we assume for now little-endian memory accesses. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-10-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:00:59 +03:00
# *** RV128I Base Instruction Set (in addition to RV64I) ***
ldu ............ ..... 111 ..... 0000011 @i
target/riscv: implement Zicboz extension The RISC-V base cache management operation (CBO) ISA extension has been ratified. It defines three extensions: Cache-Block Management, Cache-Block Prefetch and Cache-Block Zero. More information about the spec can be found at [1]. Let's start by implementing the Cache-Block Zero extension, Zicboz. It uses the cbo.zero instruction that, as with all CBO instructions that will be added later, needs to be implemented in an overlap group with the LQ instruction due to overlapping patterns. cbo.zero throws a Illegal Instruction/Virtual Instruction exception depending on CSR state. This is also the case for the remaining cbo instructions we're going to add next, so create a check_zicbo_envcfg() that will be used by all Zicbo[mz] instructions. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-24 16:25:34 +03:00
{
[
target/riscv: implement Zicbom extension Zicbom is the Cache-Block Management extension defined in the already ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1]. The extension contains three instructions: cbo.clean, cbo.flush and cbo.inval. All of them must be implemented in the same group as LQ and cbo.zero due to overlapping patterns. All these instructions can throw a Illegal Instruction/Virtual Instruction exception, similar to the existing cbo.zero. The same check_zicbo_envcfg() is used to handle these exceptions. Aside from that, these instructions also need to handle page faults and guest page faults. This is done in a new check_zicbom_access() helper. As with Zicboz, the cache block size for Zicbom is also configurable. Note that the spec determines that Zicbo[mp] and Zicboz can have different cache sizes (Section 2.7 of [1]), so we also include a 'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They are set to the same size, so unless users want to play around with the settings both sizes will be the same. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224132536.552293-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-24 16:25:35 +03:00
# *** RV32 Zicbom Standard Extension ***
cbo_clean 0000000 00001 ..... 010 00000 0001111 @sfence_vm
cbo_flush 0000000 00010 ..... 010 00000 0001111 @sfence_vm
cbo_inval 0000000 00000 ..... 010 00000 0001111 @sfence_vm
target/riscv: implement Zicboz extension The RISC-V base cache management operation (CBO) ISA extension has been ratified. It defines three extensions: Cache-Block Management, Cache-Block Prefetch and Cache-Block Zero. More information about the spec can be found at [1]. Let's start by implementing the Cache-Block Zero extension, Zicboz. It uses the cbo.zero instruction that, as with all CBO instructions that will be added later, needs to be implemented in an overlap group with the LQ instruction due to overlapping patterns. cbo.zero throws a Illegal Instruction/Virtual Instruction exception depending on CSR state. This is also the case for the remaining cbo instructions we're going to add next, so create a check_zicbo_envcfg() that will be used by all Zicbo[mz] instructions. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-24 16:25:34 +03:00
# *** RV32 Zicboz Standard Extension ***
cbo_zero 0000000 00100 ..... 010 00000 0001111 @sfence_vm
]
# *** RVI128 lq ***
lq ............ ..... 010 ..... 0001111 @i
}
target/riscv: accessors to registers upper part and 128-bit load/store Get function to retrieve the 64 top bits of a register, stored in the gprh field of the cpu state. Set function that writes the 128-bit value at once. The access to the gprh field can not be protected at compile time to make sure it is accessed only in the 128-bit version of the processor because we have no way to indicate that the misa_mxl_max field is const. The 128-bit ISA adds ldu, lq and sq. We provide support for these instructions. Note that (a) we compute only 64-bit addresses to actually access memory, cowardly utilizing the existing address translation mechanism of QEMU, and (b) we assume for now little-endian memory accesses. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-10-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:00:59 +03:00
sq ............ ..... 100 ..... 0100011 @s
target/riscv: support for 128-bit arithmetic instructions Addition of 128-bit adds and subs in their various sizes, "set if less than"s and branches. Refactored the code to have a comparison function used for both stls and branches. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-14-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:01:03 +03:00
addid ............ ..... 000 ..... 1011011 @i
target/riscv: support for 128-bit shift instructions Handling shifts for 32, 64 and 128 operation length for RV128, following the general framework for handling various olens proposed by Richard. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:01:02 +03:00
sllid 000000 ...... ..... 001 ..... 1011011 @sh6
srlid 000000 ...... ..... 101 ..... 1011011 @sh6
sraid 010000 ...... ..... 101 ..... 1011011 @sh6
target/riscv: support for 128-bit arithmetic instructions Addition of 128-bit adds and subs in their various sizes, "set if less than"s and branches. Refactored the code to have a comparison function used for both stls and branches. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-14-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:01:03 +03:00
addd 0000000 ..... ..... 000 ..... 1111011 @r
subd 0100000 ..... ..... 000 ..... 1111011 @r
target/riscv: support for 128-bit shift instructions Handling shifts for 32, 64 and 128 operation length for RV128, following the general framework for handling various olens proposed by Richard. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:01:02 +03:00
slld 0000000 ..... ..... 001 ..... 1111011 @r
srld 0000000 ..... ..... 101 ..... 1111011 @r
srad 0100000 ..... ..... 101 ..... 1111011 @r
target/riscv: accessors to registers upper part and 128-bit load/store Get function to retrieve the 64 top bits of a register, stored in the gprh field of the cpu state. Set function that writes the 128-bit value at once. The access to the gprh field can not be protected at compile time to make sure it is accessed only in the 128-bit version of the processor because we have no way to indicate that the misa_mxl_max field is const. The 128-bit ISA adds ldu, lq and sq. We provide support for these instructions. Note that (a) we compute only 64-bit addresses to actually access memory, cowardly utilizing the existing address translation mechanism of QEMU, and (b) we assume for now little-endian memory accesses. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-10-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:00:59 +03:00
target/riscv: Convert RVXM insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:48 +03:00
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
mulhu 0000001 ..... ..... 011 ..... 0110011 @r
div 0000001 ..... ..... 100 ..... 0110011 @r
divu 0000001 ..... ..... 101 ..... 0110011 @r
rem 0000001 ..... ..... 110 ..... 0110011 @r
remu 0000001 ..... ..... 111 ..... 0110011 @r
target/riscv: Convert RV32A insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:49 +03:00
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:12 +03:00
# *** RV64M Standard Extension (in addition to RV32M) ***
mulw 0000001 ..... ..... 000 ..... 0111011 @r
divw 0000001 ..... ..... 100 ..... 0111011 @r
divuw 0000001 ..... ..... 101 ..... 0111011 @r
remw 0000001 ..... ..... 110 ..... 0111011 @r
remuw 0000001 ..... ..... 111 ..... 0111011 @r
target/riscv: support for 128-bit M extension Mult are generated inline (using a cool trick pointed out by Richard), but for div and rem, given the complexity of the implementation of these instructions, we call helpers to produce their behavior. From an implementation standpoint, the helpers return the low part of the results, while the high part is temporarily stored in a dedicated field of cpu_env that is used to update the architectural register in the generation wrapper. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-15-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-07 00:01:04 +03:00
# *** RV128M Standard Extension (in addition to RV64M) ***
muld 0000001 ..... ..... 000 ..... 1111011 @r
divd 0000001 ..... ..... 100 ..... 1111011 @r
divud 0000001 ..... ..... 101 ..... 1111011 @r
remd 0000001 ..... ..... 110 ..... 1111011 @r
remud 0000001 ..... ..... 111 ..... 1111011 @r
target/riscv: Convert RV32A insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:49 +03:00
# *** RV32A Standard Extension ***
lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
target/riscv: Convert RV32F insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:51 +03:00
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:12 +03:00
# *** RV64A Standard Extension (in addition to RV32A) ***
lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
target/riscv: Convert RV32F insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:51 +03:00
# *** RV32F Standard Extension ***
flw ............ ..... 010 ..... 0000111 @i
fsw ....... ..... ..... 010 ..... 0100111 @s
fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
feq_s 1010000 ..... ..... 010 ..... 1010011 @r
flt_s 1010000 ..... ..... 001 ..... 1010011 @r
fle_s 1010000 ..... ..... 000 ..... 1010011 @r
fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
target/riscv: Convert RV32D insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:53 +03:00
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:12 +03:00
# *** RV64F Standard Extension (in addition to RV32F) ***
fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
target/riscv: Convert RV32D insns to decodetree Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-13 18:53:53 +03:00
# *** RV32D Standard Extension ***
fld ............ ..... 011 ..... 0000111 @i
fsd ....... ..... ..... 011 ..... 0100111 @s
fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
feq_d 1010001 ..... ..... 010 ..... 1010011 @r
flt_d 1010001 ..... ..... 001 ..... 1010011 @r
fle_d 1010001 ..... ..... 000 ..... 1010011 @r
fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
target/riscv: Move the hfence instructions to the rvh decode Also correct the name of the VVMA instruction. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-04-04 00:05:01 +03:00
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:12 +03:00
# *** RV64D Standard Extension (in addition to RV32D) ***
fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
target/riscv: Move the hfence instructions to the rvh decode Also correct the name of the VVMA instruction. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-04-04 00:05:01 +03:00
# *** RV32H Base Instruction Set ***
target/riscv: Allow generating hlv/hlvx/hsv instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>
2020-08-12 22:13:19 +03:00
hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
target/riscv: Move the hfence instructions to the rvh decode Also correct the name of the VVMA instruction. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-04-04 00:05:01 +03:00
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
target/riscv: add vector configure instruction vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-5-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:52 +03:00
target/riscv: Fix the RV64H decode comment BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:37 +03:00
# *** RV64H Base Instruction Set ***
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:12 +03:00
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:54 +03:00
# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
target/riscv: rvv-1.0: stride load and store instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-21-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:06 +03:00
# Vector unit-stride load/store insns.
vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-75-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:57:00 +03:00
# Vector unit-stride mask load/store insns.
vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2
vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2
target/riscv: rvv-1.0: stride load and store instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-21-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:06 +03:00
# Vector strided insns.
vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
target/riscv: rvv-1.0: index load and store instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-22-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:07 +03:00
# Vector ordered-indexed and unordered-indexed load insns.
vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
target/riscv: add vector index load and store instructions Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-8-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:55 +03:00
# Vector ordered-indexed and unordered-indexed store insns.
target/riscv: rvv-1.0: index load and store instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-22-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:07 +03:00
vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
target/riscv: add vector index load and store instructions Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-8-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:55 +03:00
target/riscv: rvv-1.0: fault-only-first unit stride load Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-24-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:09 +03:00
# Vector unit-stride fault-only-first load insns.
vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
target/riscv: rvv-1.0: load/store whole register instructions Add the following instructions: * vl<nf>re<eew>.v * vs<nf>r.v Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-25-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:10 +03:00
# Vector whole register insns
vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2
vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2
vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2
vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2
vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2
vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2
vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2
vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2
vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2
vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2
vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2
vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2
vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2
vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2
vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2
vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2
vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2
vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:54 +03:00
# *** new major opcode OP-V ***
target/riscv: vector single-width integer add and subtract Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-11-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:58 +03:00
vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm
vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm
vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm
vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm
vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm
vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector widening integer add and subtract Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-12-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:59 +03:00
vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm
vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm
vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm
vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm
vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm
vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm
vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm
vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm
vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm
vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-44-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:29 +03:00
vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
target/riscv: vector bitwise logical instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-14-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:01 +03:00
vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm
vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm
vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm
vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm
vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm
vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector single-width bit shift instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-15-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:02 +03:00
vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm
vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm
vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm
vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm
vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm
vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: rvv-1.0: narrowing integer right shift instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-45-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:30 +03:00
vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector integer comparison instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-17-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:04 +03:00
vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm
vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm
vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm
vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm
vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm
vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm
vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm
vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm
vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm
vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm
vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm
vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm
vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm
vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm
vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm
vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm
vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector integer min/max instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-18-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:05 +03:00
vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm
vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm
vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm
vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm
vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm
vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm
vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm
vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm
target/riscv: vector single-width integer multiply instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-19-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:06 +03:00
vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm
vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm
vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm
vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm
vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm
vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm
vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm
vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: vector integer divide instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-20-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:07 +03:00
vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm
vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm
vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm
vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm
vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: vector widening integer multiply instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-21-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:08 +03:00
vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm
vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm
vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: vector single-width integer multiply-add instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-22-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:09 +03:00
vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm
vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm
vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm
vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm
vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm
vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm
vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm
vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: vector widening integer multiply-add instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-23-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:10 +03:00
vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: rvv-1.0: widening integer multiply-add instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-46-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:31 +03:00
vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: vector integer merge and move instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-24-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:11 +03:00
vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
target/riscv: vector single-width saturating add and subtract Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-25-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:12 +03:00
vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm
vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm
vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm
vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm
vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm
vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm
vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
target/riscv: rvv-1.0: single-width averaging add and subtract instructions Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-42-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:27 +03:00
vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: vector single-width fractional multiply with rounding and saturation Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-27-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:14 +03:00
vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
target/riscv: vector single-width scaling shift instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-29-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:16 +03:00
vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: rvv-1.0: narrowing fixed-point clip instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-53-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:38 +03:00
vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm
vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm
vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm
vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm
vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm
vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector single-width floating-point add/subtract instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-31-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:18 +03:00
vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm
vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: vector widening floating-point add/subtract instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-32-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:19 +03:00
vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm
vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm
vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm
vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm
vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm
vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm
vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm
vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: vector single-width floating-point multiply/divide instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-33-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:20 +03:00
vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm
vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm
vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: vector widening floating-point multiply Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-34-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:21 +03:00
vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: vector single-width floating-point fused multiply-add instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-35-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:22 +03:00
vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm
vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm
vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm
vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm
vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm
vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm
vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm
vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm
vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm
vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm
vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm
vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm
vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm
vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm
vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm
vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: vector widening floating-point fused multiply-add instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-36-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:23 +03:00
vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm
vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm
vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: rvv-1.0: floating-point square-root instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-28-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:13 +03:00
vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-70-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:55 +03:00
vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-71-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:56 +03:00
vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm
target/riscv: vector floating-point min/max instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-38-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:25 +03:00
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: vector floating-point sign-injection instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-39-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:26 +03:00
vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm
vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm
vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: rvv-1.0: floating-point slide instructions Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-52-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:37 +03:00
vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm
vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: vector floating-point compare instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-40-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:27 +03:00
vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm
vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm
vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm
vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: rvv-1.0: floating-point classify instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-29-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:14 +03:00
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
target/riscv: vector floating-point merge instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-42-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:29 +03:00
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
target/riscv: rvv-1.0: floating-point/integer type-convert instructions Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-62-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:47 +03:00
vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
target/riscv: rvv-1.0: widening floating-point/integer type-convert Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-63-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:48 +03:00
vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm
vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm
vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm
vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-65-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:50 +03:00
vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
target/riscv: vector single-width integer reduction instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-46-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:33 +03:00
vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm
vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm
vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm
vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
target/riscv: vector wideing integer reduction instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-47-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:34 +03:00
vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
target/riscv: vector single-width floating-point reduction instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-48-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:35 +03:00
# Vector ordered and unordered reduction sum
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed to vf[w]redusum_vs. The distinction between ordered and unordered is also more consistent with other instructions, although there is no difference in implementation between the two for QEMU. Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220817074802.20765-2-liuyang22@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-08-17 10:48:02 +03:00
vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm
vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
target/riscv: vector single-width floating-point reduction instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-48-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:35 +03:00
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
target/riscv: vector widening floating-point reduction instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-49-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:36 +03:00
# Vector widening ordered and unordered float reduction sum
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed to vf[w]redusum_vs. The distinction between ordered and unordered is also more consistent with other instructions, although there is no difference in implementation between the two for QEMU. Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220817074802.20765-2-liuyang22@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-08-17 10:48:02 +03:00
vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
target/riscv: vector mask-register logical instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-50-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:37 +03:00
vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-76-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:57:01 +03:00
vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r
target/riscv: vector mask-register logical instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-50-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:37 +03:00
vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r
vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-76-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:57:01 +03:00
vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r
target/riscv: vector mask-register logical instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-50-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:37 +03:00
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
target/riscv: rvv-1.0: count population in mask instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-30-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:15 +03:00
vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
target/riscv: rvv-1.0: find-first-set mask bit instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-31-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:16 +03:00
vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
target/riscv: rvv-1.0: set-X-first mask bit instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-32-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:17 +03:00
vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
target/riscv: rvv-1.0: iota instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-33-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:18 +03:00
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
target/riscv: rvv-1.0: element index instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-34-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:19 +03:00
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
target/riscv: rvv-1.0: integer scalar move instructions * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-37-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:22 +03:00
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
target/riscv: rvv-1.0: floating-point scalar move instructions NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-39-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:24 +03:00
vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
target/riscv: vector slide instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-59-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:46 +03:00
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: vector register gather instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-60-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:47 +03:00
vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
target/riscv: rvv-1.0: register gather instructions * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-36-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:21 +03:00
vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
target/riscv: vector register gather instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-60-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:47 +03:00
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector compress instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-61-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:25:48 +03:00
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
target/riscv: rvv-1.0: whole register move instructions Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-40-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:25 +03:00
vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
target/riscv: vector single-width integer add and subtract Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-11-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:58 +03:00
target/riscv: rvv-1.0: integer extension instructions Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-41-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:26 +03:00
# Vector Integer Extension
vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-72-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:57 +03:00
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
target/riscv: rvv-1.0: add vsetivli instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-73-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:56:58 +03:00
vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
target/riscv: add vector configure instruction vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-5-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-01 18:24:52 +03:00
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
target/riscv: Consolidate RV32/64 32-bit instructions This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
2021-04-24 06:34:12 +03:00
RISC-V: Add Zawrs ISA extension support This patch adds support for the Zawrs ISA extension. Given the current (incomplete) implementation of reservation sets there seems to be no way to provide a full emulation of the WRS instruction (wake on reservation set invalidation or timeout or interrupt). Therefore, we just exit the TB and return to the main loop. The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Note, that the Zawrs extension is frozen, but not ratified yet. Changes since v3: * Remove "RFC" since the extension is frozen * Rebase on master and fix integration issues * Fix entry ordering in extension list Changes since v2: * Rebase on master and resolve conflicts * Adjustments according to a specification change * Inline REQUIRE_ZAWRS() since it has only one user Changes since v1: * Adding zawrs to the ISA string that is passed to the kernel Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221005144948.3421504-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-10-05 17:49:48 +03:00
# *** Zawrs Standard Extension ***
wrs_nto 000000001101 00000 000 00000 1110011
wrs_sto 000000011101 00000 000 00000 1110011
target/riscv: Reassign instructions to the Zba-extension The following instructions are part of Zba: - add.uw (RV64 only) - sh[123]add (RV32 and RV64) - sh[123]add.uw (RV64-only) - slli.uw (RV64-only) Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:05 +03:00
# *** RV32 Zba Standard Extension ***
sh1add 0010000 .......... 010 ..... 0110011 @r
sh2add 0010000 .......... 100 ..... 0110011 @r
sh3add 0010000 .......... 110 ..... 0110011 @r
# *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
add_uw 0000100 .......... 000 ..... 0111011 @r
sh1add_uw 0010000 .......... 010 ..... 0111011 @r
sh2add_uw 0010000 .......... 100 ..... 0111011 @r
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
slli_uw 00001 ............ 001 ..... 0011011 @sh
target/riscv: rvk: add support for zbkb extension - reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:34:58 +03:00
# *** RV32 Zbb/Zbkb Standard Extension ***
target/riscv: Reassign instructions to the Zbb-extension This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:10 +03:00
andn 0100000 .......... 111 ..... 0110011 @r
target/riscv: rvk: add support for zbkb extension - reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:34:58 +03:00
rol 0110000 .......... 001 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rori 01100 ............ 101 ..... 0010011 @sh
# The encoding for rev8 differs between RV32 and RV64.
# rev8_32 denotes the RV32 variant.
rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
# The encoding for zext.h differs between RV32 and RV64.
# zext_h_32 denotes the RV32 variant.
{
zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
pack 0000100 ..... ..... 100 ..... 0110011 @r
}
xnor 0100000 .......... 100 ..... 0110011 @r
# *** RV32 extra Zbb Standard Extension ***
target/riscv: rvb: count leading/trailing zeros Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 19:06:03 +03:00
clz 011000 000000 ..... 001 ..... 0010011 @r2
target/riscv: rvb: count bits set Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 19:06:04 +03:00
cpop 011000 000010 ..... 001 ..... 0010011 @r2
target/riscv: Reassign instructions to the Zbb-extension This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:10 +03:00
ctz 011000 000001 ..... 001 ..... 0010011 @r2
max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and removed gorc/gorci. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:11 +03:00
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
target/riscv: Reassign instructions to the Zbb-extension This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:10 +03:00
orn 0100000 .......... 110 ..... 0110011 @r
target/riscv: rvb: sign-extend instructions Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-8-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-05 19:06:08 +03:00
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
target/riscv: rvk: add support for zbkb extension - reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:34:58 +03:00
# *** RV32 extra Zbkb Standard Extension ***
brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
packh 0000100 .......... 111 ..... 0110011 @r
unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
target/riscv: Reassign instructions to the Zbb-extension This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:10 +03:00
target/riscv: rvk: add support for zbkb extension - reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:34:58 +03:00
# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
target/riscv: Add rev8 instruction, removing grev/grevi The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a rev8 instruction (equivalent to the rev8 pseudo-instruction built on grevi from pre-0.93 draft-B) is available. This commit adds the new rev8 instruction and removes grev/grevi. Note that there is no W-form of this instruction (both a sign-extending and zero-extending 32-bit version can easily be synthesized by following rev8 with either a srai or srli instruction on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are different. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:13 +03:00
# The encoding for rev8 differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
target/riscv: Reassign instructions to the Zbb-extension This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:10 +03:00
rolw 0110000 .......... 001 ..... 0111011 @r
roriw 0110000 .......... 101 ..... 0011011 @sh5
rorw 0110000 .......... 101 ..... 0111011 @r
target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a zext.h instruction is provided (built on pack/packh from pre-0.93 draft-B) is available. This commit adds zext.h and removes the pack* instructions. Note that the encodings for zext.h are different between RV32 and RV64, which is handled through REQUIRE_32BIT. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:14 +03:00
# The encoding for zext.h differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
target/riscv: rvk: add support for zbkb extension - reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:34:58 +03:00
{
zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
packw 0000100 ..... ..... 100 ..... 0111011 @r
}
# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
target/riscv: Reassign instructions to the Zbb-extension This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:10 +03:00
target/riscv: rvk: add support for zbkc extension - reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:34:59 +03:00
# *** RV32 Zbc/Zbkc Standard Extension ***
target/riscv: Add instructions of the Zbc-extension The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:09 +03:00
clmul 0000101 .......... 001 ..... 0110011 @r
clmulh 0000101 .......... 011 ..... 0110011 @r
target/riscv: rvk: add support for zbkc extension - reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:34:59 +03:00
# *** RV32 extra Zbc Standard Extension ***
target/riscv: Add instructions of the Zbc-extension The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:09 +03:00
clmulr 0000101 .......... 010 ..... 0110011 @r
target/riscv: rvk: add support for zbkx extension - add xperm4 and xperm8 instructions Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:00 +03:00
# *** RV32 Zbkx Standard Extension ***
xperm4 0010100 .......... 010 ..... 0110011 @r
xperm8 0010100 .......... 100 ..... 0110011 @r
target/riscv: Reassign instructions to the Zbs-extension The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 17:00:08 +03:00
# *** RV32 Zbs Standard Extension ***
bclr 0100100 .......... 001 ..... 0110011 @r
bclri 01001. ........... 001 ..... 0010011 @sh
bext 0100100 .......... 101 ..... 0110011 @r
bexti 01001. ........... 101 ..... 0010011 @sh
binv 0110100 .......... 001 ..... 0110011 @r
binvi 01101. ........... 001 ..... 0010011 @sh
bset 0010100 .......... 001 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
target/riscv: zfh: half-precision load and store Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211210074329.5775-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:43:20 +03:00
riscv: Add support for the Zfa extension This patch introduces the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of float register bigger than XLEN * Quiet comparison instructions (fleq/fltq) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) Since QEMU does not support the RISC-V quad-precision floating-point ISA extension (Q), this patch does not include the instructions that depend on this extension. All other instructions are included in this patch. The Zfa specification can be found here: https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex The Zfa specifciation is frozen and is in public review since May 3, 2023: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg The patch also includes a TCG test for the fcvtmod.w.d instruction. The test cases test for correct results and flag behaviour. Note, that the Zfa specification requires fcvtmod's flag behaviour to be identical to a fcvt with the same operands (which is also tested). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230710071243.282464-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10 10:12:43 +03:00
# *** Zfa Standard Extension ***
fli_s 1111000 00001 ..... 000 ..... 1010011 @r2
fli_d 1111001 00001 ..... 000 ..... 1010011 @r2
fli_h 1111010 00001 ..... 000 ..... 1010011 @r2
fminm_s 0010100 ..... ..... 010 ..... 1010011 @r
fmaxm_s 0010100 ..... ..... 011 ..... 1010011 @r
fminm_d 0010101 ..... ..... 010 ..... 1010011 @r
fmaxm_d 0010101 ..... ..... 011 ..... 1010011 @r
fminm_h 0010110 ..... ..... 010 ..... 1010011 @r
fmaxm_h 0010110 ..... ..... 011 ..... 1010011 @r
fround_s 0100000 00100 ..... ... ..... 1010011 @r2_rm
froundnx_s 0100000 00101 ..... ... ..... 1010011 @r2_rm
fround_d 0100001 00100 ..... ... ..... 1010011 @r2_rm
froundnx_d 0100001 00101 ..... ... ..... 1010011 @r2_rm
fround_h 0100010 00100 ..... ... ..... 1010011 @r2_rm
froundnx_h 0100010 00101 ..... ... ..... 1010011 @r2_rm
fcvtmod_w_d 1100001 01000 ..... 001 ..... 1010011 @r2
fmvh_x_d 1110001 00001 ..... 000 ..... 1010011 @r2
fmvp_d_x 1011001 ..... ..... 000 ..... 1010011 @r
fleq_s 1010000 ..... ..... 100 ..... 1010011 @r
fltq_s 1010000 ..... ..... 101 ..... 1010011 @r
fleq_d 1010001 ..... ..... 100 ..... 1010011 @r
fltq_d 1010001 ..... ..... 101 ..... 1010011 @r
fleq_h 1010010 ..... ..... 100 ..... 1010011 @r
fltq_h 1010010 ..... ..... 101 ..... 1010011 @r
target/riscv: zfh: half-precision load and store Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211210074329.5775-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:43:20 +03:00
# *** RV32 Zfh Extension ***
flh ............ ..... 001 ..... 0000111 @i
fsh ....... ..... ..... 001 ..... 0100111 @s
target/riscv: zfh: half-precision computational Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:43:21 +03:00
fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm
fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm
fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm
fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm
fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm
fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm
fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm
target/riscv: zfh: half-precision convert and move Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:43:22 +03:00
fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r
fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r
fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r
target/riscv: zfh: half-precision computational Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:43:21 +03:00
fmin_h 0010110 ..... ..... 000 ..... 1010011 @r
fmax_h 0010110 ..... ..... 001 ..... 1010011 @r
target/riscv: zfh: half-precision convert and move Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:43:22 +03:00
fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm
fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm
fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
target/riscv: zfh: half-precision floating-point compare Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-5-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:43:23 +03:00
feq_h 1010010 ..... ..... 010 ..... 1010011 @r
flt_h 1010010 ..... ..... 001 ..... 1010011 @r
fle_h 1010010 ..... ..... 000 ..... 1010011 @r
target/riscv: zfh: half-precision floating-point classify Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-6-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:43:24 +03:00
fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2
target/riscv: zfh: half-precision convert and move Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-10 10:43:22 +03:00
fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
# *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
target/riscv: add support for svinval extension - sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check - do nothing other than extension check for sfence.w.inval and sfence.inval.ir Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-04 05:26:57 +03:00
# *** Svinval Standard Extension ***
sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
sfence_w_inval 0001100 00000 00000 000 00000 1110011
sfence_inval_ir 0001100 00001 00000 000 00000 1110011
hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
target/riscv: rvk: add support for zknd/zkne extension in RV32 - add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:02 +03:00
# *** RV32 Zknd Standard Extension ***
aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
target/riscv: rvk: add support for zkne/zknd extension in RV64 - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:03 +03:00
# *** RV64 Zknd Standard Extension ***
aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
target/riscv: rvk: add support for zknd/zkne extension in RV32 - add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:02 +03:00
# *** RV32 Zkne Standard Extension ***
aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
target/riscv: rvk: add support for zkne/zknd extension in RV64 - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:03 +03:00
# *** RV64 Zkne Standard Extension ***
aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
# *** RV64 Zkne/zknd Standard Extension ***
aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
target/riscv: rvk: add support for sha256 related instructions in zknh extension - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-9-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:04 +03:00
# *** RV32 Zknh Standard Extension ***
sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension - add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:05 +03:00
sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-11-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:06 +03:00
# *** RV64 Zknh Standard Extension ***
sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
target/riscv: rvk: add support for zksed/zksh extension - add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu <luruibo2000@163.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-23 05:35:07 +03:00
# *** RV32 Zksh Standard Extension ***
sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
# *** RV32 Zksed Standard Extension ***
sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
target/riscv: Add support for Zicond extension The spec can be found in https://github.com/riscv/riscv-zicond. Two instructions are added: - czero.eqz: Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd. - czero.nez: Moves zero to a register rd, if the condition rs2 is nonzero, otherwise moves rs1 to rd. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230221091009.36545-1-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-21 12:10:09 +03:00
# *** RV32 Zicond Standard Extension ***
czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r
czero_nez 0000111 ..... ..... 111 ..... 0110011 @r
target/riscv: Add support for Zfbfmin extension Add trans_* and helper function for Zfbfmin instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230615063302.102409-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-15 09:32:58 +03:00
# *** Zfbfmin Standard Extension ***
fcvt_bf16_s 0100010 01000 ..... ... ..... 1010011 @r2_rm
fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm
target/riscv: Add support for Zvfbfmin extension Add trans_* and helper function for Zvfbfmin instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230615063302.102409-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-15 09:32:59 +03:00
# *** Zvfbfmin Standard Extension ***
vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm
vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm
target/riscv: Add support for Zvfbfwma extension Add trans_* and helper function for Zvfbfwma instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230615063302.102409-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-15 09:33:00 +03:00
# *** Zvfbfwma Standard Extension ***
vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm
vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm
target/riscv: Add Zvbc ISA extension support This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vclmulh.[vx,vv] * vclmul.[vx,vv] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Co-authored-by: Max Chou <max.chou@sifive.com> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> [max.chou@sifive.com: Exposed x-zvbc property] Message-ID: <20230711165917.2629866-5-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:03 +03:00
# *** Zvbc vector crypto extension ***
vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm
vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm
vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm
vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: Add Zvbb ISA extension support This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Co-authored-by: William Salmon <will.salmon@codethink.co.uk> Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> [max.chou@sifive.com: Fix imm mode of vror.vi] Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: William Salmon <will.salmon@codethink.co.uk> Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Exposed x-zvbb property] Message-ID: <20230711165917.2629866-9-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:07 +03:00
# *** Zvbb vector crypto extension ***
vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm
vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm
vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm
vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm
vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6
vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm
vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm
vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm
vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm
vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm
vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm
vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm
vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm
vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm
vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm
vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: Add Zvkned ISA extension support This commit adds support for the Zvkned vector-crypto extension, which consists of the following instructions: * vaesef.[vv,vs] * vaesdf.[vv,vs] * vaesdm.[vv,vs] * vaesz.vs * vaesem.[vv,vs] * vaeskf1.vi * vaeskf2.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Co-authored-by: William Salmon <will.salmon@codethink.co.uk> [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: William Salmon <will.salmon@codethink.co.uk> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned property] [max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl egs checking by helper function] [max.chou@sifive.com: Replaced bswap32 calls in aes key expanding] Message-ID: <20230711165917.2629866-10-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:08 +03:00
# *** Zvkned vector crypto extension ***
vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1
vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1
vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1
vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1
vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1
vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1
vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1
vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
target/riscv: Add Zvknh ISA extension support This commit adds support for the Zvknh vector-crypto extension, which consists of the following instructions: * vsha2ms.vv * vsha2c[hl].vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties] [max.chou@sifive.com: Replaced SEW selection to happened during translation] Message-ID: <20230711165917.2629866-11-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:09 +03:00
# *** Zvknh vector crypto extension ***
vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
target/riscv: Add Zvksh ISA extension support This commit adds support for the Zvksh vector-crypto extension, which consists of the following instructions: * vsm3me.vv * vsm3c.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Exposed x-zvksh property] Message-ID: <20230711165917.2629866-12-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:10 +03:00
# *** Zvksh vector crypto extension ***
vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1
vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
target/riscv: Add Zvkg ISA extension support This commit adds support for the Zvkg vector-crypto extension, which consists of the following instructions: * vgmul.vv * vghsh.vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> [max.chou@sifive.com: Exposed x-zvkg property] [max.chou@sifive.com: Replaced uint by int for cross win32 build] Message-ID: <20230711165917.2629866-13-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:11 +03:00
# *** Zvkg vector crypto extension ***
vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1
vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1
target/riscv: Add Zvksed ISA extension support This commit adds support for the Zvksed vector-crypto extension, which consists of the following instructions: * vsm4k.vi * vsm4r.[vv,vs] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> [lawrence.hunter@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor style changes] Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20230711165917.2629866-16-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-11 19:59:14 +03:00
# *** Zvksed vector crypto extension ***
vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1
vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1
vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1
target/riscv: Add support for Zacas extension Add support for amocas.w/d/q instructions which are part of the ratified Zacas extension: https://github.com/riscv/riscv-zacas Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231207153842.32401-2-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-12-07 18:32:30 +03:00
# *** RV32 Zacas Standard Extension ***
amocas_w 00101 . . ..... ..... 010 ..... 0101111 @atom_st
amocas_d 00101 . . ..... ..... 011 ..... 0101111 @atom_st
# *** RV64 Zacas Standard Extension ***
amocas_q 00101 . . ..... ..... 100 ..... 0101111 @atom_st
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