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target/riscv: rvk: add support for zbkx extension

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- add xperm4 and xperm8 instructions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2022-04-23 10:35:00 +08:00 committed by Alistair Francis
parent 5cc69ceb68
commit 0496389680
4 changed files with 51 additions and 0 deletions
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27
target/riscv/bitmanip_helper.c
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@ -102,3 +102,30 @@ target_ulong HELPER(zip)(target_ulong rs1)
x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
return x;
}
static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
uint32_t sz_log2)
{
target_ulong r = 0;
target_ulong sz = 1LL << sz_log2;
target_ulong mask = (1LL << sz) - 1;
target_ulong pos;
for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
pos = ((rs2 >> i) & mask) << sz_log2;
if (pos < sizeof(target_ulong) * 8) {
r |= ((rs1 >> pos) & mask) << i;
}
}
return r;
}
target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
{
return do_xperm(rs1, rs2, 2);
}
target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
{
return do_xperm(rs1, rs2, 3);
}

2
target/riscv/helper.h
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@ -69,6 +69,8 @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* Floating Point - Half Precision */
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)

4
target/riscv/insn32.decode
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@ -776,6 +776,10 @@ clmulh 0000101 .......... 011 ..... 0110011 @r
# *** RV32 extra Zbc Standard Extension ***
clmulr 0000101 .......... 010 ..... 0110011 @r
# *** RV32 Zbkx Standard Extension ***
xperm4 0010100 .......... 010 ..... 0110011 @r
xperm8 0010100 .......... 100 ..... 0110011 @r
# *** RV32 Zbs Standard Extension ***
bclr 0100100 .......... 001 ..... 0110011 @r
bclri 01001. ........... 001 ..... 0010011 @sh

18
target/riscv/insn_trans/trans_rvb.c.inc
View File

@ -48,6 +48,12 @@
} \
} while (0)
#define REQUIRE_ZBKX(ctx) do { \
if (!ctx->cfg_ptr->ext_zbkx) { \
return false; \
} \
} while (0)
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@ -574,3 +580,15 @@ static bool trans_zip(DisasContext *ctx, arg_zip *a)
REQUIRE_ZBKB(ctx);
return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
}
static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
{
REQUIRE_ZBKX(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
}
static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
{
REQUIRE_ZBKX(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
}