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target/riscv: Convert RVXM insns to decodetree

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Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2019-02-13 07:53:48 -08:00
parent 771fbe156a
commit d2e2c1e406
4 changed files with 137 additions and 9 deletions
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7
target/riscv/insn32-64.decode
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@ -36,3 +36,10 @@ subw 0100000 ..... ..... 000 ..... 0111011 @r
sllw 0000000 ..... ..... 001 ..... 0111011 @r
srlw 0000000 ..... ..... 101 ..... 0111011 @r
sraw 0100000 ..... ..... 101 ..... 0111011 @r
# *** RV64M Standard Extension (in addition to RV32M) ***
mulw 0000001 ..... ..... 000 ..... 0111011 @r
divw 0000001 ..... ..... 100 ..... 0111011 @r
divuw 0000001 ..... ..... 101 ..... 0111011 @r
remw 0000001 ..... ..... 110 ..... 0111011 @r
remuw 0000001 ..... ..... 111 ..... 0111011 @r

10
target/riscv/insn32.decode
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@ -92,3 +92,13 @@ csrrc ............ ..... 011 ..... 1110011 @csr
csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
mulhu 0000001 ..... ..... 011 ..... 0110011 @r
div 0000001 ..... ..... 100 ..... 0110011 @r
divu 0000001 ..... ..... 101 ..... 0110011 @r
rem 0000001 ..... ..... 110 ..... 0110011 @r
remu 0000001 ..... ..... 111 ..... 0110011 @r

113
target/riscv/insn_trans/trans_rvm.inc.c Normal file
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@ -0,0 +1,113 @@
/*
* RISC-V translation routines for the RV64M Standard Extension.
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_div(DisasContext *ctx, arg_div *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
return true;
}
#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
return true;
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
REQUIRE_EXT(ctx, RVM);
gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
return true;
}
#endif

16
target/riscv/translate.c
View File

@ -1841,11 +1841,18 @@ static void decode_RV32_64C(DisasContext *ctx)
EX_SH(1)
EX_SH(12)
#define REQUIRE_EXT(ctx, ext) do { \
if (!has_ext(ctx, ext)) { \
return false; \
} \
} while (0)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
static void decode_RV32_64G(DisasContext *ctx)
{
@ -1867,15 +1874,6 @@ static void decode_RV32_64G(DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
case OPC_RISC_ARITH:
#if defined(TARGET_RISCV64)
case OPC_RISC_ARITH_W:
#endif
if (rd == 0) {
break; /* NOP */
}
gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2);
break;
case OPC_RISC_FP_LOAD:
gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
break;