target/riscv: Fix the RV64H decode comment
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
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@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
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hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
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hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
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# *** RV32H Base Instruction Set ***
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# *** RV64H Base Instruction Set ***
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hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
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hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
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hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
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