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target/riscv: Add Zvksh ISA extension support

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This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:

* vsm3me.vv
* vsm3c.vi

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvksh property]
Message-ID: <20230711165917.2629866-12-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Lawrence Hunter 2023-07-12 00:59:10 +08:00 committed by Alistair Francis
parent fcf1943376
commit 2350881c44
6 changed files with 177 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
target/riscv/cpu.c
View File

@ -132,6 +132,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
@ -1280,8 +1281,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
* In principle Zve*x would also suffice here, were they supported
* in qemu
*/
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) &&
!cpu->cfg.ext_zve32f) {
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
error_setg(errp,
"Vector crypto extensions require V or Zve* extensions");
return;
@ -1882,6 +1883,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false),
DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false),
DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false),
DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false),
DEFINE_PROP_END_OF_LIST(),
};

1
target/riscv/cpu_cfg.h
View File

@ -90,6 +90,7 @@ struct RISCVCPUConfig {
bool ext_zvkned;
bool ext_zvknha;
bool ext_zvknhb;
bool ext_zvksh;
bool ext_zmmul;
bool ext_zvfbfmin;
bool ext_zvfbfwma;

3
target/riscv/helper.h
View File

@ -1270,3 +1270,6 @@ DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32)

4
target/riscv/insn32.decode
View File

@ -991,3 +991,7 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
# *** Zvksh vector crypto extension ***
vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1
vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1

31
target/riscv/insn_trans/trans_rvvk.c.inc
View File

@ -500,3 +500,34 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
}
return false;
}
/*
* Zvksh
*/
#define ZVKSH_EGS 8
static inline bool vsm3_check(DisasContext *s, arg_rmrr *a)
{
int egw_bytes = ZVKSH_EGS << s->sew;
int mult = 1 << MAX(s->lmul, 0);
return s->cfg_ptr->ext_zvksh == true &&
require_rvv(s) &&
vext_check_isa_ill(s) &&
!is_overlapped(a->rd, mult, a->rs2, mult) &&
MAXSZ(s) >= egw_bytes &&
s->sew == MO_32;
}
static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a)
{
return vsm3_check(s, a) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
}
static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a)
{
return vsm3_check(s, a) && vext_check_ss(s, a->rd, a->rs2, a->vm);
}
GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS)
GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS)

134
target/riscv/vcrypto_helper.c
View File

@ -635,3 +635,137 @@ void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env,
vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz);
env->vstart = 0;
}
static inline uint32_t p1(uint32_t x)
{
return x ^ rol32(x, 15) ^ rol32(x, 23);
}
static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3,
uint32_t m13, uint32_t m6)
{
return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6;
}
void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr,
CPURISCVState *env, uint32_t desc)
{
uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW));
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
uint32_t *vd = vd_vptr;
uint32_t *vs1 = vs1_vptr;
uint32_t *vs2 = vs2_vptr;
for (int i = env->vstart / 8; i < env->vl / 8; i++) {
uint32_t w[24];
for (int j = 0; j < 8; j++) {
w[j] = bswap32(vs1[H4((i * 8) + j)]);
w[j + 8] = bswap32(vs2[H4((i * 8) + j)]);
}
for (int j = 0; j < 8; j++) {
w[j + 16] =
zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]);
}
for (int j = 0; j < 8; j++) {
vd[(i * 8) + j] = bswap32(w[H4(j + 16)]);
}
}
vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz);
env->vstart = 0;
}
static inline uint32_t ff1(uint32_t x, uint32_t y, uint32_t z)
{
return x ^ y ^ z;
}
static inline uint32_t ff2(uint32_t x, uint32_t y, uint32_t z)
{
return (x & y) | (x & z) | (y & z);
}
static inline uint32_t ff_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j)
{
return (j <= 15) ? ff1(x, y, z) : ff2(x, y, z);
}
static inline uint32_t gg1(uint32_t x, uint32_t y, uint32_t z)
{
return x ^ y ^ z;
}
static inline uint32_t gg2(uint32_t x, uint32_t y, uint32_t z)
{
return (x & y) | (~x & z);
}
static inline uint32_t gg_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j)
{
return (j <= 15) ? gg1(x, y, z) : gg2(x, y, z);
}
static inline uint32_t t_j(uint32_t j)
{
return (j <= 15) ? 0x79cc4519 : 0x7a879d8a;
}
static inline uint32_t p_0(uint32_t x)
{
return x ^ rol32(x, 9) ^ rol32(x, 17);
}
static void sm3c(uint32_t *vd, uint32_t *vs1, uint32_t *vs2, uint32_t uimm)
{
uint32_t x0, x1;
uint32_t j;
uint32_t ss1, ss2, tt1, tt2;
x0 = vs2[0] ^ vs2[4];
x1 = vs2[1] ^ vs2[5];
j = 2 * uimm;
ss1 = rol32(rol32(vs1[0], 12) + vs1[4] + rol32(t_j(j), j % 32), 7);
ss2 = ss1 ^ rol32(vs1[0], 12);
tt1 = ff_j(vs1[0], vs1[1], vs1[2], j) + vs1[3] + ss2 + x0;
tt2 = gg_j(vs1[4], vs1[5], vs1[6], j) + vs1[7] + ss1 + vs2[0];
vs1[3] = vs1[2];
vd[3] = rol32(vs1[1], 9);
vs1[1] = vs1[0];
vd[1] = tt1;
vs1[7] = vs1[6];
vd[7] = rol32(vs1[5], 19);
vs1[5] = vs1[4];
vd[5] = p_0(tt2);
j = 2 * uimm + 1;
ss1 = rol32(rol32(vd[1], 12) + vd[5] + rol32(t_j(j), j % 32), 7);
ss2 = ss1 ^ rol32(vd[1], 12);
tt1 = ff_j(vd[1], vs1[1], vd[3], j) + vs1[3] + ss2 + x1;
tt2 = gg_j(vd[5], vs1[5], vd[7], j) + vs1[7] + ss1 + vs2[1];
vd[2] = rol32(vs1[1], 9);
vd[0] = tt1;
vd[6] = rol32(vs1[5], 19);
vd[4] = p_0(tt2);
}
void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm,
CPURISCVState *env, uint32_t desc)
{
uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW));
uint32_t total_elems = vext_get_total_elems(env, desc, esz);
uint32_t vta = vext_vta(desc);
uint32_t *vd = vd_vptr;
uint32_t *vs2 = vs2_vptr;
uint32_t v1[8], v2[8], v3[8];
for (int i = env->vstart / 8; i < env->vl / 8; i++) {
for (int k = 0; k < 8; k++) {
v2[k] = bswap32(vd[H4(i * 8 + k)]);
v3[k] = bswap32(vs2[H4(i * 8 + k)]);
}
sm3c(v1, v2, v3, uimm);
for (int k = 0; k < 8; k++) {
vd[i * 8 + k] = bswap32(v1[H4(k)]);
}
}
vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz);
env->vstart = 0;
}