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target/riscv: Add instructions of the Zbc-extension

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The following instructions are part of Zbc:
 - clmul
 - clmulh
 - clmulr

Note that these instructions were already defined in the pre-0.93 and
the 0.93 draft-B proposals, but had not been omitted in the earlier
addition of draft-B to QEmu.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich 2021-09-11 16:00:09 +02:00 committed by Alistair Francis
parent f36a4a89aa
commit fd4b81a304
4 changed files with 65 additions and 1 deletions
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27
target/riscv/bitmanip_helper.c
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@ -3,6 +3,7 @@
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
* Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@ -88,3 +89,29 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
{
return do_gorc(rs1, rs2, 32);
}
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
{
target_ulong result = 0;
for (int i = 0; i < TARGET_LONG_BITS; i++) {
if ((rs2 >> i) & 1) {
result ^= (rs1 << i);
}
}
return result;
}
target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
{
target_ulong result = 0;
for (int i = 0; i < TARGET_LONG_BITS; i++) {
if ((rs2 >> i) & 1) {
result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
}
}
return result;
}

2
target/riscv/helper.h
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@ -63,6 +63,8 @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)

5
target/riscv/insn32.decode
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@ -714,6 +714,11 @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
clmulh 0000101 .......... 011 ..... 0110011 @r
clmulr 0000101 .......... 010 ..... 0110011 @r
# *** RV32 Zbs Standard Extension ***
bclr 0100100 .......... 001 ..... 0110011 @r
bclri 01001. ........... 001 ..... 0010011 @sh

32
target/riscv/insn_trans/trans_rvb.c.inc
View File

@ -1,5 +1,5 @@
/*
* RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
* RISC-V translation routines for the Zb[acs] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@ -24,6 +24,12 @@
} \
} while (0)
#define REQUIRE_ZBC(ctx) do { \
if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBS(ctx) do { \
if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
return false; \
@ -535,3 +541,27 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
REQUIRE_ZBA(ctx);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
}
static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
{
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
}
static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_clmulr(dst, src1, src2);
tcg_gen_shri_tl(dst, dst, 1);
}
static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
{
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
}
static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
{
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
}