target/riscv: Add rev8 instruction, removing grev/grevi
The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a rev8 instruction (equivalent to the rev8 pseudo-instruction built on grevi from pre-0.93 draft-B) is available. This commit adds the new rev8 instruction and removes grev/grevi. Note that there is no W-form of this instruction (both a sign-extending and zero-extending 32-bit version can easily be synthesized by following rev8 with either a srai or srli instruction on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are different. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -24,46 +24,6 @@
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#include "exec/helper-proto.h"
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#include "tcg/tcg.h"
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static const uint64_t adjacent_masks[] = {
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dup_const(MO_8, 0x55),
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dup_const(MO_8, 0x33),
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dup_const(MO_8, 0x0f),
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dup_const(MO_16, 0xff),
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dup_const(MO_32, 0xffff),
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UINT32_MAX
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};
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static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
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{
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return ((x & mask) << shift) | ((x & ~mask) >> shift);
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}
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static target_ulong do_grev(target_ulong rs1,
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target_ulong rs2,
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int bits)
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{
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target_ulong x = rs1;
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int i, shift;
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for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
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if (rs2 & shift) {
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x = do_swap(x, adjacent_masks[i], shift);
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}
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}
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return x;
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}
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target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
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{
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return do_grev(rs1, rs2, TARGET_LONG_BITS);
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}
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target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
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{
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return do_grev(rs1, rs2, 32);
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}
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target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
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{
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target_ulong result = 0;
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@ -59,8 +59,6 @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
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DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
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/* Bitmanip */
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DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
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@ -683,6 +683,9 @@ min 0000101 .......... 100 ..... 0110011 @r
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minu 0000101 .......... 101 ..... 0110011 @r
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orc_b 001010 000111 ..... 101 ..... 0010011 @r2
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orn 0100000 .......... 110 ..... 0110011 @r
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# The encoding for rev8 differs between RV32 and RV64.
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# rev8_32 denotes the RV32 variant.
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rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
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rol 0110000 .......... 001 ..... 0110011 @r
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ror 0110000 .......... 101 ..... 0110011 @r
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rori 01100 ............ 101 ..... 0010011 @sh
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@ -694,6 +697,10 @@ xnor 0100000 .......... 100 ..... 0110011 @r
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clzw 0110000 00000 ..... 001 ..... 0011011 @r2
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ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
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cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
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# The encoding for rev8 differs between RV32 and RV64.
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# When executing on RV64, the encoding used in RV32 is an illegal
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# instruction, so we use different handler functions to differentiate.
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rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
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rolw 0110000 .......... 001 ..... 0111011 @r
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roriw 0110000 .......... 101 ..... 0011011 @sh5
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rorw 0110000 .......... 101 ..... 0111011 @r
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@ -702,15 +709,10 @@ rorw 0110000 .......... 101 ..... 0111011 @r
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pack 0000100 .......... 100 ..... 0110011 @r
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packu 0100100 .......... 100 ..... 0110011 @r
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packh 0000100 .......... 111 ..... 0110011 @r
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grev 0110100 .......... 101 ..... 0110011 @r
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grevi 01101. ........... 101 ..... 0010011 @sh
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# *** RV64B Standard Extension (in addition to RV32B) ***
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packw 0000100 .......... 100 ..... 0111011 @r
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packuw 0100100 .......... 100 ..... 0111011 @r
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grevw 0110100 .......... 101 ..... 0111011 @r
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greviw 0110100 .......... 101 ..... 0011011 @sh5
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# *** RV32 Zbc Standard Extension ***
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clmul 0000101 .......... 001 ..... 0110011 @r
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@ -273,26 +273,18 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
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return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
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}
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static bool trans_grev(DisasContext *ctx, arg_grev *a)
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static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
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REQUIRE_32BIT(ctx);
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REQUIRE_ZBB(ctx);
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return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
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}
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static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
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static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
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{
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if (shamt == TARGET_LONG_BITS - 8) {
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/* rev8, byte swaps */
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tcg_gen_bswap_tl(dest, src);
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} else {
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gen_helper_grev(dest, src, tcg_constant_tl(shamt));
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}
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}
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static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
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REQUIRE_64BIT(ctx);
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REQUIRE_ZBB(ctx);
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return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
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}
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static void gen_orc_b(TCGv ret, TCGv source1)
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@ -471,22 +463,6 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
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return gen_shift(ctx, a, EXT_NONE, gen_rolw);
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}
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static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
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}
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static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
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}
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#define GEN_SHADD_UW(SHAMT) \
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static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
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{ \
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