target/riscv: rvv-1.0: index load and store instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-22-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang
Alistair Francis
parent
79556fb6fa
commit
08b9d0ed4a
@ -136,41 +136,38 @@ DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32)
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DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32)
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DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32)
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DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32)
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DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxbu_v_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxbu_v_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxbu_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxbu_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxhu_v_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxhu_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxhu_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxwu_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxwu_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vlxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
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DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
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@ -322,18 +322,17 @@ vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
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vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
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vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
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vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
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vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
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vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
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vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
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vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
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vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
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vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
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# Vector ordered-indexed and unordered-indexed load insns.
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vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
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vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
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vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
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vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
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# Vector ordered-indexed and unordered-indexed store insns.
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vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
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vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
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vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
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vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
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vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
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vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
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vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
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vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
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# *** new major opcode OP-V ***
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vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
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@ -803,31 +803,38 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
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return true;
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}
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static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
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static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
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{
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uint32_t data = 0;
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gen_helper_ldst_index *fn;
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static gen_helper_ldst_index * const fns[7][4] = {
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{ gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
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gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
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{ NULL, gen_helper_vlxh_v_h,
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gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
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{ NULL, NULL,
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gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
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{ gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
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gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
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{ gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
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gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
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{ NULL, gen_helper_vlxhu_v_h,
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gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
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{ NULL, NULL,
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gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
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static gen_helper_ldst_index * const fns[4][4] = {
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/*
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* offset vector register group EEW = 8,
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* data vector register group EEW = SEW
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*/
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{ gen_helper_vlxei8_8_v, gen_helper_vlxei8_16_v,
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gen_helper_vlxei8_32_v, gen_helper_vlxei8_64_v },
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/*
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* offset vector register group EEW = 16,
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* data vector register group EEW = SEW
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*/
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{ gen_helper_vlxei16_8_v, gen_helper_vlxei16_16_v,
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gen_helper_vlxei16_32_v, gen_helper_vlxei16_64_v },
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/*
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* offset vector register group EEW = 32,
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* data vector register group EEW = SEW
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*/
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{ gen_helper_vlxei32_8_v, gen_helper_vlxei32_16_v,
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gen_helper_vlxei32_32_v, gen_helper_vlxei32_64_v },
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/*
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* offset vector register group EEW = 64,
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* data vector register group EEW = SEW
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*/
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{ gen_helper_vlxei64_8_v, gen_helper_vlxei64_16_v,
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gen_helper_vlxei64_32_v, gen_helper_vlxei64_64_v }
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};
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fn = fns[seq][s->sew];
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if (fn == NULL) {
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return false;
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}
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fn = fns[eew][s->sew];
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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@ -835,11 +842,6 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
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return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
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}
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/*
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* For vector indexed segment loads, the destination vector register
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* groups cannot overlap the source vector register group (specified by
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* `vs2`), else an illegal instruction exception is raised.
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*/
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static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
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{
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return require_rvv(s) &&
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@ -847,33 +849,43 @@ static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
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vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew);
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}
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GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxei8_v, MO_8, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxei16_v, MO_16, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxei32_v, MO_32, rnfvm, ld_index_op, ld_index_check)
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GEN_VEXT_TRANS(vlxei64_v, MO_64, rnfvm, ld_index_op, ld_index_check)
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static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
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static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
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{
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uint32_t data = 0;
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gen_helper_ldst_index *fn;
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static gen_helper_ldst_index * const fns[4][4] = {
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{ gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
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gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
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{ NULL, gen_helper_vsxh_v_h,
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gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
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{ NULL, NULL,
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gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
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{ gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
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gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
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/*
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* offset vector register group EEW = 8,
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* data vector register group EEW = SEW
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*/
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{ gen_helper_vsxei8_8_v, gen_helper_vsxei8_16_v,
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gen_helper_vsxei8_32_v, gen_helper_vsxei8_64_v },
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/*
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* offset vector register group EEW = 16,
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* data vector register group EEW = SEW
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*/
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{ gen_helper_vsxei16_8_v, gen_helper_vsxei16_16_v,
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gen_helper_vsxei16_32_v, gen_helper_vsxei16_64_v },
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/*
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* offset vector register group EEW = 32,
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* data vector register group EEW = SEW
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*/
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{ gen_helper_vsxei32_8_v, gen_helper_vsxei32_16_v,
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gen_helper_vsxei32_32_v, gen_helper_vsxei32_64_v },
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/*
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* offset vector register group EEW = 64,
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* data vector register group EEW = SEW
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*/
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{ gen_helper_vsxei64_8_v, gen_helper_vsxei64_16_v,
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gen_helper_vsxei64_32_v, gen_helper_vsxei64_64_v }
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};
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fn = fns[seq][s->sew];
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if (fn == NULL) {
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return false;
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}
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fn = fns[eew][s->sew];
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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@ -888,10 +900,10 @@ static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
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vext_check_st_index(s, a->rd, a->rs2, a->nf, eew);
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}
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GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxei8_v, MO_8, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxei16_v, MO_16, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxei32_v, MO_32, rnfvm, st_index_op, st_index_check)
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GEN_VEXT_TRANS(vsxei64_v, MO_64, rnfvm, st_index_op, st_index_check)
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/*
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*** unit stride fault-only-first load
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@ -217,15 +217,6 @@ static void NAME(CPURISCVState *env, abi_ptr addr, \
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cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
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}
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GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb)
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GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb)
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GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb)
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GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb)
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GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw)
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GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw)
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GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw)
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GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl)
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GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl)
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GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
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GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
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GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
|
||||
@ -393,8 +384,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
|
||||
void *vs2, CPURISCVState *env, uint32_t desc,
|
||||
vext_get_index_addr get_index_addr,
|
||||
vext_ldst_elem_fn *ldst_elem,
|
||||
uint32_t esz, uint32_t msz, uintptr_t ra,
|
||||
MMUAccessType access_type)
|
||||
uint32_t esz, uintptr_t ra, MMUAccessType access_type)
|
||||
{
|
||||
uint32_t i, k;
|
||||
uint32_t nf = vext_nf(desc);
|
||||
@ -406,7 +396,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
|
||||
if (!vm && !vext_elem_mask(v0, i)) {
|
||||
continue;
|
||||
}
|
||||
probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
|
||||
probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra,
|
||||
access_type);
|
||||
}
|
||||
/* load bytes from guest memory */
|
||||
@ -416,67 +406,63 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
|
||||
continue;
|
||||
}
|
||||
while (k < nf) {
|
||||
abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
|
||||
abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
|
||||
ldst_elem(env, addr, i + k * vlmax, vd, ra);
|
||||
k++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN) \
|
||||
#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \
|
||||
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
|
||||
void *vs2, CPURISCVState *env, uint32_t desc) \
|
||||
{ \
|
||||
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
|
||||
LOAD_FN, sizeof(ETYPE), sizeof(MTYPE), \
|
||||
GETPC(), MMU_DATA_LOAD); \
|
||||
LOAD_FN, sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
|
||||
}
|
||||
|
||||
GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b)
|
||||
GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h)
|
||||
GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w)
|
||||
GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d)
|
||||
GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h)
|
||||
GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w)
|
||||
GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d)
|
||||
GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w)
|
||||
GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d)
|
||||
GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b)
|
||||
GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h)
|
||||
GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w)
|
||||
GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d)
|
||||
GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b)
|
||||
GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h)
|
||||
GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w)
|
||||
GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d)
|
||||
GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h)
|
||||
GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w)
|
||||
GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d)
|
||||
GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w)
|
||||
GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w)
|
||||
GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w)
|
||||
GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w)
|
||||
GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w)
|
||||
GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d)
|
||||
|
||||
#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
|
||||
#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \
|
||||
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
|
||||
void *vs2, CPURISCVState *env, uint32_t desc) \
|
||||
{ \
|
||||
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
|
||||
STORE_FN, sizeof(ETYPE), sizeof(MTYPE), \
|
||||
STORE_FN, sizeof(ETYPE), \
|
||||
GETPC(), MMU_DATA_STORE); \
|
||||
}
|
||||
|
||||
GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b)
|
||||
GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h)
|
||||
GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w)
|
||||
GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d)
|
||||
GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h)
|
||||
GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w)
|
||||
GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d)
|
||||
GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w)
|
||||
GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d)
|
||||
GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
|
||||
GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
|
||||
GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
|
||||
GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w)
|
||||
GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w)
|
||||
GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w)
|
||||
GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
|
||||
GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
|
||||
|
||||
/*
|
||||
*** unit-stride fault-only-fisrt load instructions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user