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157 Commits

Author SHA1 Message Date
Stanislav Shwartsman
3d97374ce8 Some fixes for functionality 2008-09-24 10:39:35 +00:00
Stanislav Shwartsman
991ae348cb Clean invalidate_prefetch_q when not needed 2008-08-23 13:55:37 +00:00
Stanislav Shwartsman
5e92a1642d Fixed compilation errors, added BX_ASSERT in paging.cc 2008-08-18 05:20:23 +00:00
Stanislav Shwartsman
e2fa98b629 - Fixed TLB flush on CR3 change - flush all pages is CR4.PGE is OFF 2008-08-16 15:35:35 +00:00
Stanislav Shwartsman
5eb845763e Fixed corner case problem cause by my prev optimization 2008-08-15 14:30:50 +00:00
Stanislav Shwartsman
aea946b4a3 One more change to speedup memory access through HostPtr check 2008-08-14 22:26:15 +00:00
Stanislav Shwartsman
dcb82ec4bf Optimize TLB flush methods 2008-08-13 21:51:54 +00:00
Stanislav Shwartsman
cddcdccd99 Fixed paging bug 2008-08-10 20:32:00 +00:00
Stanislav Shwartsman
5dd02b26e3 Make even more efficient RmAddr calculation - good optimizing compiler could make more efficient code than it was before 2008-08-08 09:22:49 +00:00
Stanislav Shwartsman
bbf02a8bc5 More clean rewrite of the TLB access bits 2008-08-07 22:14:38 +00:00
Stanislav Shwartsman
67eb13bf24 Fixed bug in PDPE cache implementation 2008-08-04 14:46:28 +00:00
Stanislav Shwartsman
4808a0d581 Fixed accessBits algebra 2008-08-04 05:30:37 +00:00
Stanislav Shwartsman
6398ebb1d4 First step of access bits cleanup and optimization - no perf gain yet 2008-08-03 19:53:09 +00:00
Stanislav Shwartsman
67f302352c Implement PDPE cache to support faster PAE paging tranlsation 2008-08-01 13:28:44 +00:00
Stanislav Shwartsman
709d74728d Call #UD exception directly instead of UndefinedOpcode function - for future use 2008-07-13 15:35:10 +00:00
Stanislav Shwartsman
c1f308d80d Push error code if segment violation occurs when pushing arguments into a new stack 2008-06-25 02:28:31 +00:00
Stanislav Shwartsman
a0e66d0e4c fixed variable name 2008-06-14 16:55:45 +00:00
Stanislav Shwartsman
b7480b3e6f - Fixed x86 data breakpoint match when breakpoint length is 8 bytes 
- FIxed x86 data breakpoint in paging disabled mode
 2008-06-02 18:41:08 +00:00
Stanislav Shwartsman
5c75e54d45 cleanup and small optimization for non-paging mode 2008-05-30 16:58:47 +00:00
Stanislav Shwartsman
6c5f82c4c8 - Fixed bug in global pages TLB invalidation 2008-05-30 12:14:00 +00:00
Stanislav Shwartsman
d76297d01e Fixed compilation err 2008-05-23 17:58:42 +00:00
Stanislav Shwartsman
3619c0f6b4 Some changes to make x86-debugger feature working back 2008-05-23 17:49:46 +00:00
Stanislav Shwartsman
3f1e436926 Removed unused variables in bx_dbg struct 2008-05-23 14:04:45 +00:00
Stanislav Shwartsman
4e091f2a3a Improved debug prints 2008-05-21 21:38:59 +00:00
Stanislav Shwartsman
82d8e9a3b0 Fixed compilation warning 2008-05-19 20:05:03 +00:00
Stanislav Shwartsman
4e5d10d02e Code reorganization + small bug fixes in translate linear code 2008-05-19 18:10:32 +00:00
Stanislav Shwartsman
c3f96973ba Added debug prints 2008-05-12 19:19:03 +00:00
Stanislav Shwartsman
d934190370 Fixed data type for cr3_masked 2008-05-11 19:58:41 +00:00
Stanislav Shwartsman
4a76bd2169 Fixed setting of reserved bits in CR3 register 2008-05-11 19:36:06 +00:00
Stanislav Shwartsman
56a44d675b Fixed potential memory overflow in dbg paging function 2008-05-10 22:11:48 +00:00
Stanislav Shwartsman
6ebae41ad7 print physcial address with special format - preparations for 64-bit physical address emu 2008-05-09 22:33:37 +00:00
Stanislav Shwartsman
ed4be45a8b Split shift/rotate opcodes in 32-bit mode and 64-bit mode 2008-05-02 22:47:07 +00:00
Stanislav Shwartsman
67e534832b Remove from CPU reference to MEM object - it is only one and could be static 2008-04-27 19:49:02 +00:00
Stanislav Shwartsman
9047c9be96 Support for reserved bits checking in paging 
Check for page is in DTLB before invalidating by INVLPG
 2008-04-25 20:08:23 +00:00
Stanislav Shwartsman
3c7949948b - Added >32bit physical address PANIC in PSE mode with 4M paging 
- Fixed LAR/LSL instructions in 64-bit mode
 2008-04-22 22:05:38 +00:00
Stanislav Shwartsman
c09934f90a some small cleanup in paging code 2008-04-21 20:17:45 +00:00
Stanislav Shwartsman
359eb92c73 More fixes for CPU emulation 2008-04-19 20:00:28 +00:00
Stanislav Shwartsman
e10bd0b7a5 tasking - read state first and only when store state in new TSS 
paging - fixed data for trace-mem callbacks
 2008-04-19 14:13:43 +00:00
Stanislav Shwartsman
bdaef81603 Added debugger memory trace functionality. Enable by 'trace-mem on' command 2008-04-19 13:21:23 +00:00
Stanislav Shwartsman
20a8bf03ad Added comments for >32 bit physical address error message 2008-04-11 14:30:15 +00:00
Stanislav Shwartsman
fea49bb270 Fixed linear address wrap in legacy (not long64) mode 2008-04-07 18:39:17 +00:00
Stanislav Shwartsman
90f1973bef Removed BX_USE_TLB - TLB is always used, only Guest2HostTLB is optional feature 
Use Guest2HostTLB in prefetch code for IFETCHES - speedup above 3%
 2008-04-05 20:41:00 +00:00
Stanislav Shwartsman
e91409704f Convert EFER to val32 register, similar to other control registers 2008-03-31 20:56:27 +00:00
Stanislav Shwartsman
3f2487a0af Enabled tracing cross repeated instructions 2008-03-31 18:53:08 +00:00
Stanislav Shwartsman
b5f5e01f7e added assert to paging.cc 2008-03-29 21:12:11 +00:00
Stanislav Shwartsman
f3a91710e4 Split access_linear to access_read_linear and access_write_linear 2008-03-29 18:18:08 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
cdcd7522aa Added RIP to the GPR register file as lst register 
This allowed to optimize (read - remove) two more BxResolve methods in 64-bit mode
+ Some white space cleanup
 2008-02-15 19:03:54 +00:00
Stanislav Shwartsman
8d7410a852 Canonical check have higher priority than #AC check 2008-02-11 20:52:10 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00