tasking - read state first and only when store state in new TSS
paging - fixed data for trace-mem callbacks
This commit is contained in:
Stanislav Shwartsman
parent
5fafafb5e6
commit
e10bd0b7a5
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: paging.cc,v 1.119 2008-04-19 13:21:23 sshwarts Exp $
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// $Id: paging.cc,v 1.120 2008-04-19 14:13:43 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1181,7 +1181,7 @@ void BX_CPU_C::access_write_linear(bx_address laddr, unsigned len, unsigned curr
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BX_CPU_THIS_PTR address_xlation.pages = 1;
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BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, (bx_phy_address) laddr, len, BX_WRITE);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, (bx_phy_address) laddr, len,
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curr_pl, BX_WRITE, (Bit8u*) &data);
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curr_pl, BX_WRITE, (Bit8u*) data);
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#if BX_SupportGuest2HostTLB
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unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 0);
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@ -1229,7 +1229,7 @@ void BX_CPU_C::access_write_linear(bx_address laddr, unsigned len, unsigned curr
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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BX_CPU_THIS_PTR address_xlation.paddress1,
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BX_CPU_THIS_PTR address_xlation.len1, curr_pl,
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BX_WRITE, (Bit8u*) &data);
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BX_WRITE, (Bit8u*) data);
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BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS,
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BX_CPU_THIS_PTR address_xlation.paddress1,
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BX_CPU_THIS_PTR address_xlation.len1, data);
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@ -1294,7 +1294,7 @@ void BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_
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BX_CPU_THIS_PTR address_xlation.paddress1, len, xlate_rw);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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BX_CPU_THIS_PTR address_xlation.paddress1, len, curr_pl,
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BX_READ, (Bit8u*) &data);
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BX_READ, (Bit8u*) data);
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}
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else {
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// access across 2 pages
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@ -1317,7 +1317,7 @@ void BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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BX_CPU_THIS_PTR address_xlation.paddress1,
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BX_CPU_THIS_PTR address_xlation.len1, curr_pl,
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BX_READ, (Bit8u*) &data);
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BX_READ, (Bit8u*) data);
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BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress2,
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BX_CPU_THIS_PTR address_xlation.len2,
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((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
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@ -1367,7 +1367,7 @@ void BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_
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if (tlbEntry->lpf == lpf) {
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BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, (bx_phy_address) laddr, len, data);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, (bx_phy_address) laddr, len,
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curr_pl, BX_READ, (Bit8u*) &data);
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curr_pl, BX_READ, (Bit8u*) data);
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return;
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}
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// We haven't seen this page, or it's been bumped before.
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@ -1398,7 +1398,7 @@ void BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_
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BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, (bx_phy_address) laddr, len, data);
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, (bx_phy_address) laddr, len,
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curr_pl, BX_READ, (Bit8u*) &data);
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curr_pl, BX_READ, (Bit8u*) data);
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}
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else {
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// Access spans two pages.
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@ -1420,7 +1420,7 @@ void BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_
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BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr,
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BX_CPU_THIS_PTR address_xlation.paddress1,
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BX_CPU_THIS_PTR address_xlation.len1, curr_pl,
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BX_READ, (Bit8u*) &data);
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BX_READ, (Bit8u*) data);
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BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS,
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BX_CPU_THIS_PTR address_xlation.paddress2,
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BX_CPU_THIS_PTR address_xlation.len2,
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: tasking.cc,v 1.51 2008-04-19 11:08:39 sshwarts Exp $
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// $Id: tasking.cc,v 1.52 2008-04-19 14:13:43 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -216,7 +216,74 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
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// Privilege and busy checks done in CALL, JUMP, INT, IRET
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// STEP 3: Save the current task state in the TSS. Up to this point,
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// STEP 3: The new-task state is loaded from the TSS
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if (tss_descriptor->type <= 3) {
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access_read_linear(Bit32u(nbase32 + 14), 2, 0, BX_READ, &temp16);
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newEIP = temp16; // zero out upper word
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access_read_linear(Bit32u(nbase32 + 16), 2, 0, BX_READ, &temp16);
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newEFLAGS = temp16;
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// incoming TSS is 16bit:
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// - upper word of general registers is set to 0xFFFF
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// - upper word of eflags is zero'd
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// - FS, GS are zero'd
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// - upper word of eIP is zero'd
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access_read_linear(Bit32u(nbase32 + 18), 2, 0, BX_READ, &temp16);
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newEAX = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 20), 2, 0, BX_READ, &temp16);
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newECX = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 22), 2, 0, BX_READ, &temp16);
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newEDX = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 24), 2, 0, BX_READ, &temp16);
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newEBX = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 26), 2, 0, BX_READ, &temp16);
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newESP = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 28), 2, 0, BX_READ, &temp16);
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newEBP = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 30), 2, 0, BX_READ, &temp16);
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newESI = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 32), 2, 0, BX_READ, &temp16);
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newEDI = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 34), 2, 0, BX_READ, &raw_es_selector);
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access_read_linear(Bit32u(nbase32 + 36), 2, 0, BX_READ, &raw_cs_selector);
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access_read_linear(Bit32u(nbase32 + 38), 2, 0, BX_READ, &raw_ss_selector);
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access_read_linear(Bit32u(nbase32 + 40), 2, 0, BX_READ, &raw_ds_selector);
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access_read_linear(Bit32u(nbase32 + 42), 2, 0, BX_READ, &raw_ldt_selector);
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raw_fs_selector = 0; // use a NULL selector
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raw_gs_selector = 0; // use a NULL selector
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// No CR3 change for 286 task switch
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newCR3 = 0; // keep compiler happy (not used)
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trap_word = 0; // keep compiler happy (not used)
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}
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else {
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if (BX_CPU_THIS_PTR cr0.get_PG())
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access_read_linear(Bit32u(nbase32 + 0x1c), 4, 0, BX_READ, &newCR3);
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else
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newCR3 = 0; // keep compiler happy (not used)
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access_read_linear(Bit32u(nbase32 + 0x20), 4, 0, BX_READ, &newEIP);
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access_read_linear(Bit32u(nbase32 + 0x24), 4, 0, BX_READ, &newEFLAGS);
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access_read_linear(Bit32u(nbase32 + 0x28), 4, 0, BX_READ, &newEAX);
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access_read_linear(Bit32u(nbase32 + 0x2c), 4, 0, BX_READ, &newECX);
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access_read_linear(Bit32u(nbase32 + 0x30), 4, 0, BX_READ, &newEDX);
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access_read_linear(Bit32u(nbase32 + 0x34), 4, 0, BX_READ, &newEBX);
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access_read_linear(Bit32u(nbase32 + 0x38), 4, 0, BX_READ, &newESP);
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access_read_linear(Bit32u(nbase32 + 0x3c), 4, 0, BX_READ, &newEBP);
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access_read_linear(Bit32u(nbase32 + 0x40), 4, 0, BX_READ, &newESI);
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access_read_linear(Bit32u(nbase32 + 0x44), 4, 0, BX_READ, &newEDI);
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access_read_linear(Bit32u(nbase32 + 0x48), 2, 0, BX_READ, &raw_es_selector);
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access_read_linear(Bit32u(nbase32 + 0x4c), 2, 0, BX_READ, &raw_cs_selector);
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access_read_linear(Bit32u(nbase32 + 0x50), 2, 0, BX_READ, &raw_ss_selector);
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access_read_linear(Bit32u(nbase32 + 0x54), 2, 0, BX_READ, &raw_ds_selector);
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access_read_linear(Bit32u(nbase32 + 0x58), 2, 0, BX_READ, &raw_fs_selector);
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access_read_linear(Bit32u(nbase32 + 0x5c), 2, 0, BX_READ, &raw_gs_selector);
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access_read_linear(Bit32u(nbase32 + 0x60), 2, 0, BX_READ, &raw_ldt_selector);
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access_read_linear(Bit32u(nbase32 + 0x64), 2, 0, BX_READ, &trap_word);
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}
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// STEP 4: Save the current task state in the TSS. Up to this point,
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// any exception that occurs aborts the task switch without
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// changing the processor state.
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@ -284,73 +351,6 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
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access_write_linear(nbase32, 2, 0, &temp16);
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}
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// STEP 4: The new-task state is loaded from the TSS
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if (tss_descriptor->type <= 3) {
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access_read_linear(Bit32u(nbase32 + 14), 2, 0, BX_READ, &temp16);
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newEIP = temp16; // zero out upper word
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access_read_linear(Bit32u(nbase32 + 16), 2, 0, BX_READ, &temp16);
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newEFLAGS = temp16;
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// incoming TSS is 16bit:
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// - upper word of general registers is set to 0xFFFF
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// - upper word of eflags is zero'd
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// - FS, GS are zero'd
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// - upper word of eIP is zero'd
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access_read_linear(Bit32u(nbase32 + 18), 2, 0, BX_READ, &temp16);
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newEAX = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 20), 2, 0, BX_READ, &temp16);
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newECX = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 22), 2, 0, BX_READ, &temp16);
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newEDX = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 24), 2, 0, BX_READ, &temp16);
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newEBX = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 26), 2, 0, BX_READ, &temp16);
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newESP = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 28), 2, 0, BX_READ, &temp16);
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newEBP = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 30), 2, 0, BX_READ, &temp16);
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newESI = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 32), 2, 0, BX_READ, &temp16);
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newEDI = 0xffff0000 | temp16;
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access_read_linear(Bit32u(nbase32 + 34), 2, 0, BX_READ, &raw_es_selector);
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access_read_linear(Bit32u(nbase32 + 36), 2, 0, BX_READ, &raw_cs_selector);
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access_read_linear(Bit32u(nbase32 + 38), 2, 0, BX_READ, &raw_ss_selector);
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access_read_linear(Bit32u(nbase32 + 40), 2, 0, BX_READ, &raw_ds_selector);
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access_read_linear(Bit32u(nbase32 + 42), 2, 0, BX_READ, &raw_ldt_selector);
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raw_fs_selector = 0; // use a NULL selector
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raw_gs_selector = 0; // use a NULL selector
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// No CR3 change for 286 task switch
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newCR3 = 0; // keep compiler happy (not used)
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trap_word = 0; // keep compiler happy (not used)
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}
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else {
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if (BX_CPU_THIS_PTR cr0.get_PG())
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access_read_linear(Bit32u(nbase32 + 0x1c), 4, 0, BX_READ, &newCR3);
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else
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newCR3 = 0; // keep compiler happy (not used)
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access_read_linear(Bit32u(nbase32 + 0x20), 4, 0, BX_READ, &newEIP);
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access_read_linear(Bit32u(nbase32 + 0x24), 4, 0, BX_READ, &newEFLAGS);
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access_read_linear(Bit32u(nbase32 + 0x28), 4, 0, BX_READ, &newEAX);
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access_read_linear(Bit32u(nbase32 + 0x2c), 4, 0, BX_READ, &newECX);
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access_read_linear(Bit32u(nbase32 + 0x30), 4, 0, BX_READ, &newEDX);
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access_read_linear(Bit32u(nbase32 + 0x34), 4, 0, BX_READ, &newEBX);
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access_read_linear(Bit32u(nbase32 + 0x38), 4, 0, BX_READ, &newESP);
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access_read_linear(Bit32u(nbase32 + 0x3c), 4, 0, BX_READ, &newEBP);
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access_read_linear(Bit32u(nbase32 + 0x40), 4, 0, BX_READ, &newESI);
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access_read_linear(Bit32u(nbase32 + 0x44), 4, 0, BX_READ, &newEDI);
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access_read_linear(Bit32u(nbase32 + 0x48), 2, 0, BX_READ, &raw_es_selector);
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access_read_linear(Bit32u(nbase32 + 0x4c), 2, 0, BX_READ, &raw_cs_selector);
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access_read_linear(Bit32u(nbase32 + 0x50), 2, 0, BX_READ, &raw_ss_selector);
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access_read_linear(Bit32u(nbase32 + 0x54), 2, 0, BX_READ, &raw_ds_selector);
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access_read_linear(Bit32u(nbase32 + 0x58), 2, 0, BX_READ, &raw_fs_selector);
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access_read_linear(Bit32u(nbase32 + 0x5c), 2, 0, BX_READ, &raw_gs_selector);
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access_read_linear(Bit32u(nbase32 + 0x60), 2, 0, BX_READ, &raw_ldt_selector);
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access_read_linear(Bit32u(nbase32 + 0x64), 2, 0, BX_READ, &trap_word);
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}
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// Step 5: If CALL, interrupt, or JMP, set busy flag in new task's
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// TSS descriptor. If IRET, leave set.
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