print physcial address with special format - preparations for 64-bit physical address emu
This commit is contained in:
Stanislav Shwartsman
parent
8e7cf2bf3a
commit
6ebae41ad7
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: bochs.h,v 1.227 2008-04-19 13:21:21 sshwarts Exp $
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// $Id: bochs.h,v 1.228 2008-05-09 22:33:36 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -416,6 +416,9 @@ BOCHSAPI extern logfunc_t *genlog;
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#define FMT_ADDRX FMT_ADDRX32
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#endif
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#define FMT_PHY_ADDRX FMT_ADDRX32
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#define FMT_LIN_ADDRX FMT_ADDRX
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#if BX_GDBSTUB
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// defines for GDB stub
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void bx_gdbstub_init(void);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dbg_main.cc,v 1.141 2008-05-03 21:32:01 sshwarts Exp $
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// $Id: dbg_main.cc,v 1.142 2008-05-09 22:33:36 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -519,7 +519,7 @@ void bx_dbg_lin_memory_access(unsigned cpu, bx_address lin, bx_phy_address phy,
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if (! BX_CPU(dbg_cpu)->trace_mem)
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return;
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dbg_printf("[CPU%d %s]: LIN 0x" FMT_ADDRX " PHY 0x%08x (len=%d, pl=%d)",
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dbg_printf("[CPU%d %s]: LIN 0x" FMT_ADDRX " PHY 0x" FMT_PHY_ADDRX " (len=%d, pl=%d)",
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cpu,
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(rw == BX_READ) ? "RD" : (rw == BX_WRITE) ? "WR" : "??",
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lin, phy,
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@ -550,7 +550,7 @@ void bx_dbg_phy_memory_access(unsigned cpu, bx_phy_address phy, unsigned len, un
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if (! BX_CPU(dbg_cpu)->trace_mem)
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return;
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dbg_printf("[CPU%d %s]: PHY 0x%08x (len=%d)",
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dbg_printf("[CPU%d %s]: PHY 0x " FMT_PHY_ADDRX " (len=%d)",
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cpu,
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(rw == BX_READ) ? "RD" : (rw == BX_WRITE) ? "WR" : "??",
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phy,
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@ -660,7 +660,7 @@ void bx_dbg_info_control_regs_command(void)
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{
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Bit32u cr0 = SIM->get_param_num("CR0", dbg_cpu_list)->get();
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bx_address cr2 = (bx_address) SIM->get_param_num("CR2", dbg_cpu_list)->get64();
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bx_phy_address cr3 = (bx_phy_address) SIM->get_param_num("CR3", dbg_cpu_list)->get();
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bx_phy_address cr3 = (bx_phy_address) SIM->get_param_num("CR3", dbg_cpu_list)->get64();
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dbg_printf("CR0=0x%08x\n", cr0);
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dbg_printf(" PG=paging=%d\n", (cr0>>31) & 1);
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dbg_printf(" CD=cache disable=%d\n", (cr0>>30) & 1);
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@ -674,7 +674,7 @@ void bx_dbg_info_control_regs_command(void)
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dbg_printf(" MP=monitor coprocessor=%d\n", (cr0>>1) & 1);
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dbg_printf(" PE=protection enable=%d\n", (cr0>>0) & 1);
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dbg_printf("CR2=page fault linear address=0x" FMT_ADDRX "\n", cr2);
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dbg_printf("CR3=0x%08x\n", cr3);
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dbg_printf("CR3=0x " FMT_PHY_ADDRX "\n", cr3);
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dbg_printf(" PCD=page-level cache disable=%d\n", (cr3>>4) & 1);
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dbg_printf(" PWT=page-level writes transparent=%d\n", (cr3>>3) & 1);
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#if BX_CPU_LEVEL >= 4
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@ -1061,7 +1061,7 @@ next_page:
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paddr_valid = BX_CPU(which_cpu)->dbg_xlate_linear2phy(laddr, &paddr);
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if (paddr_valid) {
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if (! BX_MEM(0)->dbg_fetch_mem(BX_CPU(which_cpu), paddr, read_len, buf)) {
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dbg_printf("bx_dbg_read_linear: physical memory read error (phy=0x%08x, lin=0x" FMT_ADDRX ")\n", paddr, laddr);
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dbg_printf("bx_dbg_read_linear: physical memory read error (phy=0x" FMT_PHY_ADDRX ", lin=0x" FMT_ADDRX ")\n", paddr, laddr);
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return 0;
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}
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}
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@ -1173,7 +1173,7 @@ void bx_dbg_xlate_address(bx_lin_address laddr)
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bx_bool paddr_valid = BX_CPU(dbg_cpu)->dbg_xlate_linear2phy(laddr, &paddr);
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if (paddr_valid) {
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dbg_printf("linear page 0x" FMT_ADDRX " maps to physical page 0x%08x\n", laddr, paddr);
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dbg_printf("linear page 0x" FMT_ADDRX " maps to physical page 0x" FMT_PHY_ADDRX "\n", laddr, paddr);
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}
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else {
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dbg_printf("physical address not available for linear 0x" FMT_ADDRX "\n", laddr);
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@ -1359,7 +1359,7 @@ int bx_dbg_show_symbolic(void)
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}
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if(last_cr3 != BX_CPU(dbg_cpu)->cr3)
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dbg_printf(FMT_TICK ": address space switched. CR3: 0x%08x\n",
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dbg_printf(FMT_TICK ": address space switched. CR3: 0x" FMT_PHY_ADDRX "\n",
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bx_pc_system.time_ticks(), BX_CPU(dbg_cpu)->cr3);
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}
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@ -1406,7 +1406,7 @@ int bx_dbg_show_symbolic(void)
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BX_CPU(dbg_cpu)->guard_found.laddr);
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if (!valid) dbg_printf(" phys not valid");
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else {
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dbg_printf(" (phy: 0x%08x) %s", phy,
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dbg_printf(" (phy: 0x" FMT_PHY_ADDRX ") %s", phy,
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bx_dbg_symbolic_address(BX_CPU(dbg_cpu)->cr3,
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BX_CPU(dbg_cpu)->guard_found.eip,
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BX_CPU(dbg_cpu)->guard_found.laddr - BX_CPU(dbg_cpu)->guard_found.eip));
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@ -1489,17 +1489,17 @@ void bx_dbg_watch(int read, bx_phy_address address)
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for (i = 0; i < num_read_watchpoints; i++) {
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Bit8u buf[2];
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if (BX_MEM(0)->dbg_fetch_mem(BX_CPU(dbg_cpu), read_watchpoint[i], 2, buf))
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dbg_printf("read %08x (%04x)\n",
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dbg_printf("read 0x"FMT_PHY_ADDRX" (%04x)\n",
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read_watchpoint[i], (int)buf[0] | ((int)buf[1] << 8));
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else
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dbg_printf("read %08x (read error)\n", read_watchpoint[i]);
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dbg_printf("read 0x"FMT_PHY_ADDRX" (read error)\n", read_watchpoint[i]);
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}
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for (i = 0; i < num_write_watchpoints; i++) {
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Bit8u buf[2];
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if (BX_MEM(0)->dbg_fetch_mem(BX_CPU(dbg_cpu), write_watchpoint[i], 2, buf))
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dbg_printf("write %08x (%04x)\n", write_watchpoint[i], (int)buf[0] | ((int)buf[1] << 8));
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dbg_printf("write 0x"FMT_PHY_ADDRX" (%04x)\n", write_watchpoint[i], (int)buf[0] | ((int)buf[1] << 8));
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else
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dbg_printf("write %08x (read error)\n", write_watchpoint[i]);
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dbg_printf("write 0x"FMT_PHY_ADDRX" (read error)\n", write_watchpoint[i]);
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}
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} else {
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if (read) {
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@ -1508,14 +1508,14 @@ void bx_dbg_watch(int read, bx_phy_address address)
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return;
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}
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read_watchpoint[num_read_watchpoints++] = address;
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dbg_printf("Read watchpoint at 0x%08x inserted\n", address);
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dbg_printf("Read watchpoint at 0x" FMT_PHY_ADDRX " inserted\n", address);
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} else {
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if (num_write_watchpoints == MAX_WRITE_WATCHPOINTS) {
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dbg_printf("Too many write watchpoints\n");
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return;
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}
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write_watchpoint[num_write_watchpoints++] = address;
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dbg_printf("Write watchpoint at 0x%08x inserted\n", address);
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dbg_printf("Write watchpoint at 0x" FMT_PHY_ADDRX " inserted\n", address);
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}
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}
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}
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@ -1713,7 +1713,7 @@ void bx_dbg_disassemble_current(int which_cpu, int print_time)
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dbg_printf("(%u) ", which_cpu);
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if (BX_CPU(which_cpu)->protected_mode()) {
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dbg_printf("[0x%08x] %04x:" FMT_ADDRX " (%s): ",
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dbg_printf("[0x"FMT_PHY_ADDRX"] %04x:" FMT_ADDRX " (%s): ",
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phy, BX_CPU(which_cpu)->guard_found.cs,
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BX_CPU(which_cpu)->guard_found.eip,
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bx_dbg_symbolic_address((BX_CPU(which_cpu)->cr3) >> 12,
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@ -1721,7 +1721,7 @@ void bx_dbg_disassemble_current(int which_cpu, int print_time)
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BX_CPU(which_cpu)->get_segment_base(BX_SEG_REG_CS)));
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}
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else { // Real & V86 mode
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dbg_printf("[0x%08x] %04x:%04x (%s): ",
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dbg_printf("[0x"FMT_PHY_ADDRX"] %04x:%04x (%s): ",
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phy, BX_CPU(which_cpu)->guard_found.cs,
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(unsigned) BX_CPU(which_cpu)->guard_found.eip,
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bx_dbg_symbolic_address_16bit(BX_CPU(which_cpu)->guard_found.eip,
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@ -1779,10 +1779,10 @@ void bx_dbg_print_guard_results(void)
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dbg_printf("(%u) Caught time breakpoint\n", cpu);
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break;
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case STOP_READ_WATCH_POINT:
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dbg_printf("(%u) Caught read watch point at %08X\n", cpu, BX_CPU(cpu)->watchpoint);
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dbg_printf("(%u) Caught read watch point at 0x" FMT_PHY_ADDRX "\n", cpu, BX_CPU(cpu)->watchpoint);
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break;
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case STOP_WRITE_WATCH_POINT:
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dbg_printf("(%u) Caught write watch point at %08X\n", cpu, BX_CPU(cpu)->watchpoint);
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dbg_printf("(%u) Caught write watch point at 0x" FMT_PHY_ADDRX "\n", cpu, BX_CPU(cpu)->watchpoint);
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break;
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case STOP_MAGIC_BREAK_POINT:
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dbg_printf("(%u) Magic breakpoint\n", cpu);
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@ -1799,7 +1799,7 @@ void bx_dbg_print_guard_results(void)
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if (bx_debugger.auto_disassemble) {
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if (cpu==0) {
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// print this only once
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dbg_printf("Next at t=" FMT_LL "d\n", bx_pc_system.time_ticks ());
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dbg_printf("Next at t=" FMT_LL "d\n", bx_pc_system.time_ticks());
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}
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bx_dbg_disassemble_current(cpu, 0); // one cpu, don't print time
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}
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@ -2102,7 +2102,7 @@ void bx_dbg_info_bpoints_command(void)
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dbg_printf("pbreakpoint ");
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dbg_printf("keep ");
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dbg_printf(bx_guard.iaddr.phy[i].enabled?"y ":"n ");
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dbg_printf("0x%08x\n", bx_guard.iaddr.phy[i].addr);
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dbg_printf("0x"FMT_PHY_ADDRX"\n", bx_guard.iaddr.phy[i].addr);
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}
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#endif
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}
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@ -2770,14 +2770,14 @@ void bx_dbg_print_descriptor(unsigned char desc[8], int verbose)
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// either a code or a data segment. bit 11 (type file MSB) then says
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// 0=data segment, 1=code seg
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if (type&8) {
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dbg_printf("Code segment, linearaddr=%08x, limit=%05x %s, %s%s%s, %d-bit\n",
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dbg_printf("Code segment, laddr=%08x, limit=%05x %s, %s%s%s, %d-bit\n",
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base, limit, g ? "* 4Kbytes" : "bytes",
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(type&2)? "Execute/Read" : "Execute-Only",
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(type&4)? ", Conforming" : "",
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(type&1)? ", Accessed" : "",
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d_b ? 32 : 16);
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} else {
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dbg_printf("Data segment, linearaddr=%08x, limit=%05x %s, %s%s%s\n",
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dbg_printf("Data segment, laddr=%08x, limit=%05x %s, %s%s%s\n",
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base, limit, g ? "* 4Kbytes" : "bytes",
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(type&2)? "Read/Write" : "Read-Only",
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(type&4)? ", Expand-down" : "",
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@ -3272,7 +3272,7 @@ void bx_dbg_dump_table(void)
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return;
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}
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printf("cr3: 0x%08x\n", BX_CPU(dbg_cpu)->cr3);
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printf("cr3: 0x"FMT_PHY_ADDRX"\n", BX_CPU(dbg_cpu)->cr3);
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lin = 0;
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phy = 0;
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@ -3284,14 +3284,14 @@ void bx_dbg_dump_table(void)
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if(valid) {
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if((lin - start_lin) != (phy - start_phy)) {
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if(start_lin != 1)
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dbg_printf("0x%08x-0x%08x -> 0x%08x-0x%08x\n",
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dbg_printf("0x%08x-0x%08x -> 0x"FMT_PHY_ADDRX"-0x"FMT_PHY_ADDRX"\n",
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start_lin, lin - 1, start_phy, start_phy + (lin-1-start_lin));
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start_lin = lin;
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start_phy = phy;
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}
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} else {
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if(start_lin != 1)
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dbg_printf("0x%08x-0x%08x -> 0x%08x-0x%08x\n",
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dbg_printf("0x%08x-0x%08x -> 0x"FMT_PHY_ADDRX"-0x"FMT_PHY_ADDRX"\n",
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start_lin, lin - 1, start_phy, start_phy + (lin-1-start_lin));
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start_lin = 1;
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start_phy = 2;
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@ -3301,7 +3301,7 @@ void bx_dbg_dump_table(void)
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lin += 0x1000;
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}
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if(start_lin != 1)
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dbg_printf("0x%08x-0x%08x -> 0x%08x-0x%08x\n",
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dbg_printf("0x%08x-0x%08x -> 0x"FMT_PHY_ADDRX"-0x"FMT_PHY_ADDRX"\n",
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start_lin, 0xffffffff, start_phy, start_phy + (0xffffffff-start_lin));
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: apic.cc,v 1.107 2008-02-15 19:03:53 sshwarts Exp $
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// $Id: apic.cc,v 1.108 2008-05-09 22:33:36 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2002 Zwane Mwaikambo, Stanislav Shwartsman
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@ -179,7 +179,7 @@ void bx_generic_apic_c::set_base(bx_phy_address newbase)
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newbase &= (~0xfff);
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base_addr = newbase;
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if (id != APIC_UNKNOWN_ID)
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BX_INFO(("relocate APIC id=%d to 0x%08x", id, newbase));
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BX_INFO(("relocate APIC id=%d to 0x" FMT_PHY_ADDRX, id, newbase));
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}
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void bx_generic_apic_c::set_id(Bit8u newid)
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@ -192,7 +192,7 @@ bx_bool bx_generic_apic_c::is_selected(bx_phy_address addr, unsigned len)
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{
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if((addr & ~0xfff) == get_base()) {
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if((addr & 0xf) != 0)
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BX_INFO(("warning: misaligned APIC access. addr=0x%08x, len=%d", addr, len));
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BX_INFO(("warning: misaligned APIC access. addr=0x" FMT_PHY_ADDRX ", len=%d", addr, len));
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return 1;
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}
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return 0;
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@ -201,7 +201,7 @@ bx_bool bx_generic_apic_c::is_selected(bx_phy_address addr, unsigned len)
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void bx_generic_apic_c::read(bx_phy_address addr, void *data, unsigned len)
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{
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if((addr & ~0x3) != ((addr+len-1) & ~0x3)) {
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BX_PANIC(("APIC read at address 0x%08x spans 32-bit boundary !", addr));
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BX_PANIC(("APIC read at address 0x" FMT_PHY_ADDRX " spans 32-bit boundary !", addr));
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return;
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}
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Bit32u value;
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@ -217,13 +217,13 @@ void bx_generic_apic_c::read(bx_phy_address addr, void *data, unsigned len)
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else if (len == 2)
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*((Bit16u *)data) = value & 0xffff;
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else
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BX_PANIC(("Unsupported APIC read at address 0x%08x, len=%d", addr, len));
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BX_PANIC(("Unsupported APIC read at address 0x" FMT_PHY_ADDRX ", len=%d", addr, len));
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}
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void bx_generic_apic_c::write(bx_phy_address addr, void *data, unsigned len)
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{
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if((addr & ~0x3) != ((addr+len-1) & ~0x3)) {
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BX_PANIC(("APIC write at address 0x%08x spans 32-bit boundary !", addr));
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BX_PANIC(("APIC write at address 0x" FMT_PHY_ADDRX " spans 32-bit boundary !", addr));
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return;
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}
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bx_phy_address addr_aligned = addr & ~0x3;
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@ -246,7 +246,7 @@ void bx_generic_apic_c::write(bx_phy_address addr, void *data, unsigned len)
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value |= (*((Bit16u *)data) << shift);
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}
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else {
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BX_PANIC(("Unsupported APIC write at address 0x%08x, len=%d", addr, len));
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BX_PANIC(("Unsupported APIC write at address 0x" FMT_PHY_ADDRX ", len=%d", addr, len));
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}
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write_aligned(addr_aligned, &value);
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}
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@ -335,11 +335,11 @@ void bx_local_apic_c::set_id(Bit8u newid)
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// APIC write: 4 byte write to 16-byte aligned APIC address
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void bx_local_apic_c::write_aligned(bx_phy_address addr, Bit32u *data)
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{
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BX_DEBUG(("%s: LAPIC write 0x%08x to address %08x", cpu->name, *data, addr));
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BX_DEBUG(("%s: LAPIC write 0x" FMT_PHY_ADDRX " to address %08x", cpu->name, *data, addr));
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BX_ASSERT((addr & 0xf) == 0);
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addr &= 0xff0;
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Bit32u apic_reg = addr & 0xff0;
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Bit32u value = *data;
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switch(addr) {
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switch(apic_reg) {
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case 0x20: // local APIC id
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id = (value>>24) & APIC_ID_MASK;
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break;
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@ -423,12 +423,12 @@ void bx_local_apic_c::write_aligned(bx_phy_address addr, Bit32u *data)
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// current count for timer
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case 0x390:
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// all read-only registers should fall into this line
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BX_INFO(("warning: write to read-only APIC register 0x%02x", addr));
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BX_INFO(("warning: write to read-only APIC register 0x%x", apic_reg));
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break;
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default:
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shadow_error_status |= APIC_ERR_ILLEGAL_ADDR;
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// but for now I want to know about it in case I missed some.
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BX_PANIC(("APIC register %08x not implemented", addr));
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BX_PANIC(("APIC register %x not implemented", apic_reg));
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}
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}
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|
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@ -481,7 +481,7 @@ void bx_local_apic_c::send_ipi(void)
|
||||
|
||||
void bx_local_apic_c::write_spurious_interrupt_register(Bit32u value)
|
||||
{
|
||||
BX_DEBUG(("write %08x to spurious interrupt register", value));
|
||||
BX_DEBUG(("write of %08x to spurious interrupt register", value));
|
||||
|
||||
#ifdef BX_IMPLEMENT_XAPIC
|
||||
spurious_vector = value & 0xff;
|
||||
@ -529,7 +529,7 @@ void bx_local_apic_c::startup_msg(Bit32u vector)
|
||||
cpu->gen_reg[BX_32BIT_REG_EIP].dword.erx = 0;
|
||||
cpu->load_seg_reg(&cpu->sregs[BX_SEG_REG_CS], vector*0x100);
|
||||
BX_INFO(("%s started up at %04X:%08X by APIC",
|
||||
cpu->name, vector*0x100, cpu->gen_reg[BX_32BIT_REG_EIP].dword.erx));
|
||||
cpu->name, vector*0x100, cpu->get_eip()));
|
||||
} else {
|
||||
BX_INFO(("%s started up by APIC, but was not halted at the time", cpu->name));
|
||||
}
|
||||
@ -538,11 +538,11 @@ void bx_local_apic_c::startup_msg(Bit32u vector)
|
||||
// APIC read: 4 byte read from 16-byte aligned APIC address
|
||||
void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
|
||||
{
|
||||
BX_DEBUG(("%s: LAPIC read from address %08x", cpu->name, addr));
|
||||
BX_DEBUG(("%s: LAPIC read from address 0x" FMT_PHY_ADDRX, cpu->name, addr));
|
||||
BX_ASSERT((addr & 0xf) == 0);
|
||||
*data = 0; // default value for unimplemented registers
|
||||
bx_phy_address addr2 = addr & 0xff0;
|
||||
switch(addr2) {
|
||||
bx_phy_address apic_reg = addr & 0xff0;
|
||||
switch(apic_reg) {
|
||||
case 0x20: // local APIC id
|
||||
*data = (id) << 24; break;
|
||||
case 0x30: // local APIC version
|
||||
@ -577,7 +577,7 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
|
||||
case 0x140: case 0x150:
|
||||
case 0x160: case 0x170:
|
||||
{
|
||||
unsigned index = (addr2 - 0x100) << 1;
|
||||
unsigned index = (apic_reg - 0x100) << 1;
|
||||
Bit32u value = 0, mask = 1;
|
||||
for(int i=0;i<32;i++) {
|
||||
if(isr[index+i]) value |= mask;
|
||||
@ -591,7 +591,7 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
|
||||
case 0x1c0: case 0x1d0:
|
||||
case 0x1e0: case 0x1f0:
|
||||
{
|
||||
unsigned index = (addr2 - 0x180) << 1;
|
||||
unsigned index = (apic_reg - 0x180) << 1;
|
||||
Bit32u value = 0, mask = 1;
|
||||
for(int i=0;i<32;i++) {
|
||||
if(tmr[index+i]) value |= mask;
|
||||
@ -605,7 +605,7 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
|
||||
case 0x240: case 0x250:
|
||||
case 0x260: case 0x270:
|
||||
{
|
||||
unsigned index = (addr2 - 0x200) << 1;
|
||||
unsigned index = (apic_reg - 0x200) << 1;
|
||||
Bit32u value = 0, mask = 1;
|
||||
for(int i=0;i<32;i++) {
|
||||
if(irr[index+i]) value |= mask;
|
||||
@ -627,7 +627,7 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
|
||||
case 0x360: // LVT Lint1 Reg
|
||||
case 0x370: // LVT Error Reg
|
||||
{
|
||||
int index = (addr2 - 0x320) >> 4;
|
||||
int index = (apic_reg - 0x320) >> 4;
|
||||
*data = lvt[index];
|
||||
break;
|
||||
}
|
||||
@ -638,10 +638,8 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
|
||||
if(timer_active==0) {
|
||||
*data = timer_current;
|
||||
} else {
|
||||
Bit64u delta64;
|
||||
Bit32u delta32;
|
||||
delta64 = (bx_pc_system.time_ticks() - ticksInitial) / timer_divide_factor;
|
||||
delta32 = (Bit32u) delta64;
|
||||
Bit64u delta64 = (bx_pc_system.time_ticks() - ticksInitial) / timer_divide_factor;
|
||||
Bit32u delta32 = (Bit32u) delta64;
|
||||
if(delta32 > timer_initial)
|
||||
BX_PANIC(("APIC: R(curr timer count): delta < initial"));
|
||||
timer_current = timer_initial - delta32;
|
||||
@ -652,10 +650,10 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
|
||||
*data = timer_divconf;
|
||||
break;
|
||||
default:
|
||||
BX_INFO(("APIC register %08x not implemented", addr));
|
||||
BX_INFO(("APIC register %08x not implemented", apic_reg));
|
||||
}
|
||||
|
||||
BX_DEBUG(("%s: read from APIC address %08x = %08x", cpu->name, addr, *data));
|
||||
BX_DEBUG(("%s: read from APIC address 0x" FMT_PHY_ADDRX " = %08x", cpu->name, addr, *data));
|
||||
}
|
||||
|
||||
int bx_local_apic_c::highest_priority_int(Bit8u *array)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: cpu.cc,v 1.227 2008-05-04 05:37:36 sshwarts Exp $
|
||||
// $Id: cpu.cc,v 1.228 2008-05-09 22:33:36 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -668,10 +668,10 @@ void BX_CPU_C::prefetch(void)
|
||||
// Sanity checks
|
||||
if (! BX_CPU_THIS_PTR eipFetchPtr) {
|
||||
if (pAddr >= BX_MEM(0)->get_memory_len()) {
|
||||
BX_PANIC(("prefetch: running in bogus memory, pAddr=0x%08x", pAddr));
|
||||
BX_PANIC(("prefetch: running in bogus memory, pAddr=0x" FMT_PHY_ADDRX, pAddr));
|
||||
}
|
||||
else {
|
||||
BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x%08x", pAddr));
|
||||
BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x" FMT_PHY_ADDRX, pAddr));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: paging.cc,v 1.126 2008-05-02 22:47:07 sshwarts Exp $
|
||||
// $Id: paging.cc,v 1.127 2008-05-09 22:33:36 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -449,8 +449,8 @@ BX_CPU_C::pagingCR4Changed(Bit32u oldCR4, Bit32u newCR4)
|
||||
BX_CPU_C::CR3_change(bx_phy_address value)
|
||||
{
|
||||
if (bx_dbg.paging) {
|
||||
BX_INFO(("CR3_change(): flush TLB cache"));
|
||||
BX_INFO(("Page Directory Base %08x", (unsigned) value));
|
||||
BX_DEBUG(("CR3_change(): flush TLB cache"));
|
||||
BX_DEBUG(("Page Directory Base: 0x" FMT_PHY_ADDRX, value));
|
||||
}
|
||||
|
||||
// flush TLB even if value does not change
|
||||
@ -657,11 +657,7 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
|
||||
// generate an exception if one is warranted.
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
BX_DEBUG(("page walk for address 0x%08x:%08x", GET32H(laddr), GET32L(laddr)));
|
||||
#else
|
||||
BX_DEBUG(("page walk for address 0x%08x", laddr));
|
||||
#endif
|
||||
BX_DEBUG(("page walk for address 0x" FMT_LIN_ADDRX, laddr));
|
||||
|
||||
InstrTLB_Increment(tlbMisses);
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: proc_ctrl.cc,v 1.226 2008-05-09 08:28:00 sshwarts Exp $
|
||||
// $Id: proc_ctrl.cc,v 1.227 2008-05-09 22:33:36 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -618,11 +618,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
|
||||
SetCR0(val_32);
|
||||
break;
|
||||
case 2: /* CR2 */
|
||||
BX_DEBUG(("MOV_CdRd:CR2 = %08x", (unsigned) val_32));
|
||||
BX_DEBUG(("MOV_CdRd:CR2 = %08x", val_32));
|
||||
BX_CPU_THIS_PTR cr2 = val_32;
|
||||
break;
|
||||
case 3: // CR3
|
||||
BX_DEBUG(("MOV_CdRd:CR3 = %08x", (unsigned) val_32));
|
||||
BX_DEBUG(("MOV_CdRd:CR3 = %08x", val_32));
|
||||
// Reserved bits take on value of MOV instruction
|
||||
CR3_change(val_32);
|
||||
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR3, val_32);
|
||||
@ -728,13 +728,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
|
||||
SetCR0((Bit32u) val_64);
|
||||
break;
|
||||
case 2: /* CR2 */
|
||||
BX_DEBUG(("MOV_CqRq: write to CR2 of %08x:%08x",
|
||||
(Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF)));
|
||||
BX_DEBUG(("MOV_CqRq: write to CR2 of %08x:%08x", GET32H(val_64), GET32L(val_64)));
|
||||
BX_CPU_THIS_PTR cr2 = val_64;
|
||||
break;
|
||||
case 3: // CR3
|
||||
BX_DEBUG(("MOV_CqRq: write to CR3 of %08x:%08x",
|
||||
(Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF)));
|
||||
BX_DEBUG(("MOV_CqRq: write to CR3 of %08x:%08x", GET32H(val_64), GET32L(val_64)));
|
||||
if (val_64 & BX_CONST64(0xffffffff00000000)) {
|
||||
BX_PANIC(("CR3 write: Only 32 bit physical address space is emulated !"));
|
||||
}
|
||||
@ -745,8 +743,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
|
||||
case 4: // CR4
|
||||
// Protected mode: #GP(0) if attempt to write a 1 to
|
||||
// any reserved bit of CR4
|
||||
BX_DEBUG(("MOV_CqRq: write to CR4 of %08x:%08x",
|
||||
(Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF)));
|
||||
BX_DEBUG(("MOV_CqRq: write to CR4 of %08x:%08x", GET32H(val_64), GET32L(val_64)));
|
||||
if (! SetCR4(val_64))
|
||||
exception(BX_GP_EXCEPTION, 0, 0);
|
||||
break;
|
||||
@ -2023,7 +2020,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MWAIT(bxInstruction_c *i)
|
||||
bx_pc_system.invlpg(BX_CPU_THIS_PTR monitor.monitor_begin);
|
||||
if ((BX_CPU_THIS_PTR monitor.monitor_end & ~0xfff) != (BX_CPU_THIS_PTR monitor.monitor_begin & ~0xfff))
|
||||
bx_pc_system.invlpg(BX_CPU_THIS_PTR monitor.monitor_end);
|
||||
BX_DEBUG(("MWAIT for phys_addr=%08x", BX_CPU_THIS_PTR monitor.monitor_begin));
|
||||
BX_DEBUG(("MWAIT for phys_addr=" FMT_PHY_ADDRX, BX_CPU_THIS_PTR monitor.monitor_begin));
|
||||
BX_MEM(0)->set_monitor(BX_CPU_THIS_PTR bx_cpuid);
|
||||
|
||||
// stops instruction execution and places the processor in a optimized
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: tasking.cc,v 1.57 2008-04-28 18:14:50 sshwarts Exp $
|
||||
// $Id: tasking.cc,v 1.58 2008-05-09 22:33:36 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -421,7 +421,7 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
|
||||
// change CR3 only if it actually modified
|
||||
if (newCR3 != BX_CPU_THIS_PTR cr3) {
|
||||
CR3_change(newCR3); // Tell paging unit about new cr3 value
|
||||
BX_DEBUG (("task_switch changing CR3 to 0x%08x", newCR3));
|
||||
BX_DEBUG (("task_switch changing CR3 to 0x" FMT_PHY_ADDRX, newCR3));
|
||||
BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_TASKSWITCH, newCR3);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: memory.cc,v 1.67 2008-05-02 23:18:51 sshwarts Exp $
|
||||
// $Id: memory.cc,v 1.68 2008-05-09 22:33:37 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001 MandrakeSoft S.A.
|
||||
@ -52,7 +52,7 @@ void BX_MEM_C::writePhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned le
|
||||
|
||||
// Note: accesses should always be contained within a single page now
|
||||
if ((addr>>12) != ((addr+len-1)>>12)) {
|
||||
BX_PANIC(("writePhysicalPage: cross page access at address 0x%08x, len=%d", addr, len));
|
||||
BX_PANIC(("writePhysicalPage: cross page access at address 0x" FMT_PHY_ADDRX ", len=%d", addr, len));
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_MONITOR_MWAIT
|
||||
@ -185,13 +185,13 @@ mem_write:
|
||||
{
|
||||
switch (DEV_pci_wr_memtype(a20addr)) {
|
||||
case 0x1: // Writes to ShadowRAM
|
||||
BX_DEBUG(("Writing to ShadowRAM: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
|
||||
BX_DEBUG(("Writing to ShadowRAM: address 0x" FMT_PHY_ADDRX ", data %02x", a20addr, *data_ptr));
|
||||
*(BX_MEM_THIS get_vector(a20addr)) = *data_ptr;
|
||||
BX_DBG_DIRTY_PAGE(a20addr >> 12);
|
||||
break;
|
||||
|
||||
case 0x0: // Writes to ROM, Inhibit
|
||||
BX_DEBUG(("Write to ROM ignored: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
|
||||
BX_DEBUG(("Write to ROM ignored: address 0x" FMT_PHY_ADDRX ", data %02x", a20addr, *data_ptr));
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -212,7 +212,7 @@ inc_one:
|
||||
}
|
||||
else {
|
||||
// access outside limits of physical memory, ignore
|
||||
BX_DEBUG(("Write outside the limits of physical memory (0x%08x) (ignore)", a20addr));
|
||||
BX_DEBUG(("Write outside the limits of physical memory (0x"FMT_PHY_ADDRX") (ignore)", a20addr));
|
||||
}
|
||||
}
|
||||
|
||||
@ -224,7 +224,7 @@ void BX_MEM_C::readPhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned len
|
||||
|
||||
// Note: accesses should always be contained within a single page now
|
||||
if ((addr>>12) != ((addr+len-1)>>12)) {
|
||||
BX_PANIC(("readPhysicalPage: cross page access at address 0x%08x, len=%d", addr, len));
|
||||
BX_PANIC(("readPhysicalPage: cross page access at address 0x" FMT_PHY_ADDRX ", len=%d", addr, len));
|
||||
}
|
||||
|
||||
if (cpu != NULL) {
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: misc_mem.cc,v 1.113 2008-05-01 20:28:36 sshwarts Exp $
|
||||
// $Id: misc_mem.cc,v 1.114 2008-05-09 22:33:37 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2002 MandrakeSoft S.A.
|
||||
@ -76,7 +76,7 @@ void BX_MEM_C::init_memory(Bit32u memsize)
|
||||
{
|
||||
unsigned idx;
|
||||
|
||||
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.113 2008-05-01 20:28:36 sshwarts Exp $"));
|
||||
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.114 2008-05-09 22:33:37 sshwarts Exp $"));
|
||||
|
||||
if (BX_MEM_THIS actual_vector != NULL) {
|
||||
BX_INFO (("freeing existing memory vector"));
|
||||
@ -637,7 +637,7 @@ BX_MEM_C::registerMemoryHandlers(void *param, memory_handler_t read_handler,
|
||||
return 0;
|
||||
if (!read_handler || !write_handler)
|
||||
return 0;
|
||||
BX_INFO(("Register memory access handlers: %08x-%08x", begin_addr, end_addr));
|
||||
BX_INFO(("Register memory access handlers: 0x" FMT_PHY_ADDRX " - 0x" FMT_PHY_ADDRX, begin_addr, end_addr));
|
||||
for (unsigned page_idx = begin_addr >> 20; page_idx <= end_addr >> 20; page_idx++) {
|
||||
struct memory_handler_struct *memory_handler = new struct memory_handler_struct;
|
||||
memory_handler->next = BX_MEM_THIS memory_handlers[page_idx];
|
||||
@ -656,7 +656,7 @@ BX_MEM_C::unregisterMemoryHandlers(memory_handler_t read_handler, memory_handler
|
||||
bx_phy_address begin_addr, bx_phy_address end_addr)
|
||||
{
|
||||
bx_bool ret = 1;
|
||||
BX_INFO(("Memory access handlers unregistered: %08x-%08x", begin_addr, end_addr));
|
||||
BX_INFO(("Memory access handlers unregistered: 0x" FMT_PHY_ADDRX " - 0x" FMT_PHY_ADDRX, begin_addr, end_addr));
|
||||
for (unsigned page_idx = begin_addr >> 20; page_idx <= end_addr >> 20; page_idx++) {
|
||||
struct memory_handler_struct *memory_handler = BX_MEM_THIS memory_handlers[page_idx];
|
||||
struct memory_handler_struct *prev = NULL;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user