diff --git a/bochs/bochs.h b/bochs/bochs.h
index 3a54d3358..ee022ba8b 100644
--- a/bochs/bochs.h
+++ b/bochs/bochs.h
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: bochs.h,v 1.227 2008-04-19 13:21:21 sshwarts Exp $
+// $Id: bochs.h,v 1.228 2008-05-09 22:33:36 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2002  MandrakeSoft S.A.
@@ -416,6 +416,9 @@ BOCHSAPI extern logfunc_t *genlog;
 #define FMT_ADDRX FMT_ADDRX32
 #endif
 
+#define FMT_PHY_ADDRX FMT_ADDRX32
+#define FMT_LIN_ADDRX FMT_ADDRX
+
 #if BX_GDBSTUB
 // defines for GDB stub
 void bx_gdbstub_init(void);
diff --git a/bochs/bx_debug/dbg_main.cc b/bochs/bx_debug/dbg_main.cc
index d6f565143..d411e5d43 100644
--- a/bochs/bx_debug/dbg_main.cc
+++ b/bochs/bx_debug/dbg_main.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: dbg_main.cc,v 1.141 2008-05-03 21:32:01 sshwarts Exp $
+// $Id: dbg_main.cc,v 1.142 2008-05-09 22:33:36 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -519,7 +519,7 @@ void bx_dbg_lin_memory_access(unsigned cpu, bx_address lin, bx_phy_address phy,
   if (! BX_CPU(dbg_cpu)->trace_mem)
     return;
 
-  dbg_printf("[CPU%d %s]: LIN 0x" FMT_ADDRX " PHY 0x%08x (len=%d, pl=%d)",
+  dbg_printf("[CPU%d %s]: LIN 0x" FMT_ADDRX " PHY 0x" FMT_PHY_ADDRX " (len=%d, pl=%d)",
      cpu, 
      (rw == BX_READ) ? "RD" : (rw == BX_WRITE) ? "WR" : "??",
      lin, phy,
@@ -550,7 +550,7 @@ void bx_dbg_phy_memory_access(unsigned cpu, bx_phy_address phy, unsigned len, un
   if (! BX_CPU(dbg_cpu)->trace_mem)
     return;
 
-  dbg_printf("[CPU%d %s]: PHY 0x%08x (len=%d)",
+  dbg_printf("[CPU%d %s]: PHY 0x " FMT_PHY_ADDRX " (len=%d)",
      cpu, 
      (rw == BX_READ) ? "RD" : (rw == BX_WRITE) ? "WR" : "??",
      phy,
@@ -660,7 +660,7 @@ void bx_dbg_info_control_regs_command(void)
 {
   Bit32u cr0 = SIM->get_param_num("CR0", dbg_cpu_list)->get();
   bx_address cr2 = (bx_address) SIM->get_param_num("CR2", dbg_cpu_list)->get64();
-  bx_phy_address cr3 = (bx_phy_address) SIM->get_param_num("CR3", dbg_cpu_list)->get();
+  bx_phy_address cr3 = (bx_phy_address) SIM->get_param_num("CR3", dbg_cpu_list)->get64();
   dbg_printf("CR0=0x%08x\n", cr0);
   dbg_printf("    PG=paging=%d\n", (cr0>>31) & 1);
   dbg_printf("    CD=cache disable=%d\n", (cr0>>30) & 1);
@@ -674,7 +674,7 @@ void bx_dbg_info_control_regs_command(void)
   dbg_printf("    MP=monitor coprocessor=%d\n", (cr0>>1) & 1);
   dbg_printf("    PE=protection enable=%d\n", (cr0>>0) & 1);
   dbg_printf("CR2=page fault linear address=0x" FMT_ADDRX "\n", cr2);
-  dbg_printf("CR3=0x%08x\n", cr3);
+  dbg_printf("CR3=0x " FMT_PHY_ADDRX "\n", cr3);
   dbg_printf("    PCD=page-level cache disable=%d\n", (cr3>>4) & 1);
   dbg_printf("    PWT=page-level writes transparent=%d\n", (cr3>>3) & 1);
 #if BX_CPU_LEVEL >= 4
@@ -1061,7 +1061,7 @@ next_page:
   paddr_valid = BX_CPU(which_cpu)->dbg_xlate_linear2phy(laddr, &paddr);
   if (paddr_valid) {
     if (! BX_MEM(0)->dbg_fetch_mem(BX_CPU(which_cpu), paddr, read_len, buf)) {
-      dbg_printf("bx_dbg_read_linear: physical memory read error (phy=0x%08x, lin=0x" FMT_ADDRX ")\n", paddr, laddr);
+      dbg_printf("bx_dbg_read_linear: physical memory read error (phy=0x" FMT_PHY_ADDRX ", lin=0x" FMT_ADDRX ")\n", paddr, laddr);
       return 0;
     }
   }
@@ -1173,7 +1173,7 @@ void bx_dbg_xlate_address(bx_lin_address laddr)
 
   bx_bool paddr_valid = BX_CPU(dbg_cpu)->dbg_xlate_linear2phy(laddr, &paddr);
   if (paddr_valid) {
-    dbg_printf("linear page 0x" FMT_ADDRX " maps to physical page 0x%08x\n", laddr, paddr);
+    dbg_printf("linear page 0x" FMT_ADDRX " maps to physical page 0x" FMT_PHY_ADDRX "\n", laddr, paddr);
   }
   else {
     dbg_printf("physical address not available for linear 0x" FMT_ADDRX "\n", laddr);
@@ -1359,7 +1359,7 @@ int bx_dbg_show_symbolic(void)
     }
 
     if(last_cr3 != BX_CPU(dbg_cpu)->cr3)
-      dbg_printf(FMT_TICK ": address space switched. CR3: 0x%08x\n",
+      dbg_printf(FMT_TICK ": address space switched. CR3: 0x" FMT_PHY_ADDRX "\n",
         bx_pc_system.time_ticks(), BX_CPU(dbg_cpu)->cr3);
   }
 
@@ -1406,7 +1406,7 @@ int bx_dbg_show_symbolic(void)
         BX_CPU(dbg_cpu)->guard_found.laddr);
       if (!valid) dbg_printf(" phys not valid");
       else {
-        dbg_printf(" (phy: 0x%08x) %s", phy,
+        dbg_printf(" (phy: 0x" FMT_PHY_ADDRX ") %s", phy,
           bx_dbg_symbolic_address(BX_CPU(dbg_cpu)->cr3,
               BX_CPU(dbg_cpu)->guard_found.eip,
               BX_CPU(dbg_cpu)->guard_found.laddr - BX_CPU(dbg_cpu)->guard_found.eip));
@@ -1489,17 +1489,17 @@ void bx_dbg_watch(int read, bx_phy_address address)
     for (i = 0; i < num_read_watchpoints; i++) {
       Bit8u buf[2];
       if (BX_MEM(0)->dbg_fetch_mem(BX_CPU(dbg_cpu), read_watchpoint[i], 2, buf))
-        dbg_printf("read   %08x   (%04x)\n",
+        dbg_printf("read   0x"FMT_PHY_ADDRX"   (%04x)\n",
             read_watchpoint[i], (int)buf[0] | ((int)buf[1] << 8));
       else
-        dbg_printf("read   %08x   (read error)\n", read_watchpoint[i]);
+        dbg_printf("read   0x"FMT_PHY_ADDRX"   (read error)\n", read_watchpoint[i]);
     }
     for (i = 0; i < num_write_watchpoints; i++) {
       Bit8u buf[2];
       if (BX_MEM(0)->dbg_fetch_mem(BX_CPU(dbg_cpu), write_watchpoint[i], 2, buf))
-        dbg_printf("write  %08x   (%04x)\n", write_watchpoint[i], (int)buf[0] | ((int)buf[1] << 8));
+        dbg_printf("write  0x"FMT_PHY_ADDRX"   (%04x)\n", write_watchpoint[i], (int)buf[0] | ((int)buf[1] << 8));
       else
-        dbg_printf("write  %08x   (read error)\n", write_watchpoint[i]);
+        dbg_printf("write  0x"FMT_PHY_ADDRX"   (read error)\n", write_watchpoint[i]);
     }
   } else {
     if (read) {
@@ -1508,14 +1508,14 @@ void bx_dbg_watch(int read, bx_phy_address address)
         return;
       }
       read_watchpoint[num_read_watchpoints++] = address;
-      dbg_printf("Read watchpoint at 0x%08x inserted\n", address);
+      dbg_printf("Read watchpoint at 0x" FMT_PHY_ADDRX " inserted\n", address);
     } else {
       if (num_write_watchpoints == MAX_WRITE_WATCHPOINTS) {
         dbg_printf("Too many write watchpoints\n");
         return;
       }
       write_watchpoint[num_write_watchpoints++] = address;
-      dbg_printf("Write watchpoint at 0x%08x inserted\n", address);
+      dbg_printf("Write watchpoint at 0x" FMT_PHY_ADDRX " inserted\n", address);
     }
   }
 }
@@ -1713,7 +1713,7 @@ void bx_dbg_disassemble_current(int which_cpu, int print_time)
       dbg_printf("(%u) ", which_cpu);
 
     if (BX_CPU(which_cpu)->protected_mode()) {
-      dbg_printf("[0x%08x] %04x:" FMT_ADDRX " (%s): ",
+      dbg_printf("[0x"FMT_PHY_ADDRX"] %04x:" FMT_ADDRX " (%s): ",
         phy, BX_CPU(which_cpu)->guard_found.cs,
         BX_CPU(which_cpu)->guard_found.eip,
         bx_dbg_symbolic_address((BX_CPU(which_cpu)->cr3) >> 12,
@@ -1721,7 +1721,7 @@ void bx_dbg_disassemble_current(int which_cpu, int print_time)
            BX_CPU(which_cpu)->get_segment_base(BX_SEG_REG_CS)));
     }
     else { // Real & V86 mode
-      dbg_printf("[0x%08x] %04x:%04x (%s): ",
+      dbg_printf("[0x"FMT_PHY_ADDRX"] %04x:%04x (%s): ",
         phy, BX_CPU(which_cpu)->guard_found.cs,
         (unsigned) BX_CPU(which_cpu)->guard_found.eip,
         bx_dbg_symbolic_address_16bit(BX_CPU(which_cpu)->guard_found.eip,
@@ -1779,10 +1779,10 @@ void bx_dbg_print_guard_results(void)
         dbg_printf("(%u) Caught time breakpoint\n", cpu);
         break;
     case STOP_READ_WATCH_POINT:
-        dbg_printf("(%u) Caught read watch point at %08X\n", cpu, BX_CPU(cpu)->watchpoint);
+        dbg_printf("(%u) Caught read watch point at 0x" FMT_PHY_ADDRX "\n", cpu, BX_CPU(cpu)->watchpoint);
         break;
     case STOP_WRITE_WATCH_POINT:
-        dbg_printf("(%u) Caught write watch point at %08X\n", cpu, BX_CPU(cpu)->watchpoint);
+        dbg_printf("(%u) Caught write watch point at 0x" FMT_PHY_ADDRX "\n", cpu, BX_CPU(cpu)->watchpoint);
         break;
     case STOP_MAGIC_BREAK_POINT:
         dbg_printf("(%u) Magic breakpoint\n", cpu);
@@ -1799,7 +1799,7 @@ void bx_dbg_print_guard_results(void)
     if (bx_debugger.auto_disassemble) {
       if (cpu==0) {
         // print this only once
-        dbg_printf("Next at t=" FMT_LL "d\n", bx_pc_system.time_ticks ());
+        dbg_printf("Next at t=" FMT_LL "d\n", bx_pc_system.time_ticks());
       }
       bx_dbg_disassemble_current(cpu, 0);  // one cpu, don't print time
     }
@@ -2102,7 +2102,7 @@ void bx_dbg_info_bpoints_command(void)
     dbg_printf("pbreakpoint    ");
     dbg_printf("keep ");
     dbg_printf(bx_guard.iaddr.phy[i].enabled?"y   ":"n   ");
-    dbg_printf("0x%08x\n", bx_guard.iaddr.phy[i].addr);
+    dbg_printf("0x"FMT_PHY_ADDRX"\n", bx_guard.iaddr.phy[i].addr);
   }
 #endif
 }
@@ -2770,14 +2770,14 @@ void bx_dbg_print_descriptor(unsigned char desc[8], int verbose)
     // either a code or a data segment. bit 11 (type file MSB) then says
     // 0=data segment, 1=code seg
     if (type&8) {
-      dbg_printf("Code segment, linearaddr=%08x, limit=%05x %s, %s%s%s, %d-bit\n",
+      dbg_printf("Code segment, laddr=%08x, limit=%05x %s, %s%s%s, %d-bit\n",
         base, limit, g ? "* 4Kbytes" : "bytes",
         (type&2)? "Execute/Read" : "Execute-Only",
         (type&4)? ", Conforming" : "",
         (type&1)? ", Accessed" : "",
         d_b ? 32 : 16);
     } else {
-      dbg_printf("Data segment, linearaddr=%08x, limit=%05x %s, %s%s%s\n",
+      dbg_printf("Data segment, laddr=%08x, limit=%05x %s, %s%s%s\n",
         base, limit, g ? "* 4Kbytes" : "bytes",
         (type&2)? "Read/Write" : "Read-Only",
         (type&4)? ", Expand-down" : "",
@@ -3272,7 +3272,7 @@ void bx_dbg_dump_table(void)
     return;
   }
 
-  printf("cr3: 0x%08x\n", BX_CPU(dbg_cpu)->cr3);
+  printf("cr3: 0x"FMT_PHY_ADDRX"\n", BX_CPU(dbg_cpu)->cr3);
 
   lin = 0;
   phy = 0;
@@ -3284,14 +3284,14 @@ void bx_dbg_dump_table(void)
     if(valid) {
       if((lin - start_lin) != (phy - start_phy)) {
         if(start_lin != 1)
-          dbg_printf("0x%08x-0x%08x -> 0x%08x-0x%08x\n",
+          dbg_printf("0x%08x-0x%08x -> 0x"FMT_PHY_ADDRX"-0x"FMT_PHY_ADDRX"\n",
             start_lin, lin - 1, start_phy, start_phy + (lin-1-start_lin));
         start_lin = lin;
         start_phy = phy;
       }
     } else {
       if(start_lin != 1)
-        dbg_printf("0x%08x-0x%08x -> 0x%08x-0x%08x\n",
+        dbg_printf("0x%08x-0x%08x -> 0x"FMT_PHY_ADDRX"-0x"FMT_PHY_ADDRX"\n",
           start_lin, lin - 1, start_phy, start_phy + (lin-1-start_lin));
       start_lin = 1;
       start_phy = 2;
@@ -3301,7 +3301,7 @@ void bx_dbg_dump_table(void)
     lin += 0x1000;
   }
   if(start_lin != 1)
-    dbg_printf("0x%08x-0x%08x -> 0x%08x-0x%08x\n",
+    dbg_printf("0x%08x-0x%08x -> 0x"FMT_PHY_ADDRX"-0x"FMT_PHY_ADDRX"\n",
          start_lin, 0xffffffff, start_phy, start_phy + (0xffffffff-start_lin));
 }
 
diff --git a/bochs/cpu/apic.cc b/bochs/cpu/apic.cc
index 7d5677327..aa03aa6fb 100644
--- a/bochs/cpu/apic.cc
+++ b/bochs/cpu/apic.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: apic.cc,v 1.107 2008-02-15 19:03:53 sshwarts Exp $
+// $Id: apic.cc,v 1.108 2008-05-09 22:33:36 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (c) 2002 Zwane Mwaikambo, Stanislav Shwartsman
@@ -179,7 +179,7 @@ void bx_generic_apic_c::set_base(bx_phy_address newbase)
   newbase &= (~0xfff);
   base_addr = newbase;
   if (id != APIC_UNKNOWN_ID)
-    BX_INFO(("relocate APIC id=%d to 0x%08x", id, newbase));
+    BX_INFO(("relocate APIC id=%d to 0x" FMT_PHY_ADDRX, id, newbase));
 }
 
 void bx_generic_apic_c::set_id(Bit8u newid)
@@ -192,7 +192,7 @@ bx_bool bx_generic_apic_c::is_selected(bx_phy_address addr, unsigned len)
 {
   if((addr & ~0xfff) == get_base()) {
     if((addr & 0xf) != 0)
-      BX_INFO(("warning: misaligned APIC access. addr=0x%08x, len=%d", addr, len));
+      BX_INFO(("warning: misaligned APIC access. addr=0x" FMT_PHY_ADDRX ", len=%d", addr, len));
     return 1;
   }
   return 0;
@@ -201,7 +201,7 @@ bx_bool bx_generic_apic_c::is_selected(bx_phy_address addr, unsigned len)
 void bx_generic_apic_c::read(bx_phy_address addr, void *data, unsigned len)
 {
   if((addr & ~0x3) != ((addr+len-1) & ~0x3)) {
-    BX_PANIC(("APIC read at address 0x%08x spans 32-bit boundary !", addr));
+    BX_PANIC(("APIC read at address 0x" FMT_PHY_ADDRX " spans 32-bit boundary !", addr));
     return;
   }
   Bit32u value;
@@ -217,13 +217,13 @@ void bx_generic_apic_c::read(bx_phy_address addr, void *data, unsigned len)
   else if (len == 2)
     *((Bit16u *)data) = value & 0xffff;
   else
-    BX_PANIC(("Unsupported APIC read at address 0x%08x, len=%d", addr, len));
+    BX_PANIC(("Unsupported APIC read at address 0x" FMT_PHY_ADDRX ", len=%d", addr, len));
 }
 
 void bx_generic_apic_c::write(bx_phy_address addr, void *data, unsigned len)
 {
   if((addr & ~0x3) != ((addr+len-1) & ~0x3)) {
-    BX_PANIC(("APIC write at address 0x%08x spans 32-bit boundary !", addr));
+    BX_PANIC(("APIC write at address 0x" FMT_PHY_ADDRX " spans 32-bit boundary !", addr));
     return;
   }
   bx_phy_address addr_aligned = addr & ~0x3;
@@ -246,7 +246,7 @@ void bx_generic_apic_c::write(bx_phy_address addr, void *data, unsigned len)
     value |= (*((Bit16u *)data) << shift);
   }
   else {
-    BX_PANIC(("Unsupported APIC write at address 0x%08x, len=%d", addr, len));
+    BX_PANIC(("Unsupported APIC write at address 0x" FMT_PHY_ADDRX ", len=%d", addr, len));
   }
   write_aligned(addr_aligned, &value);
 }
@@ -335,11 +335,11 @@ void bx_local_apic_c::set_id(Bit8u newid)
 // APIC write: 4 byte write to 16-byte aligned APIC address
 void bx_local_apic_c::write_aligned(bx_phy_address addr, Bit32u *data)
 {
-  BX_DEBUG(("%s: LAPIC write 0x%08x to address %08x", cpu->name, *data, addr));
+  BX_DEBUG(("%s: LAPIC write 0x" FMT_PHY_ADDRX " to address %08x", cpu->name, *data, addr));
   BX_ASSERT((addr & 0xf) == 0);
-  addr &= 0xff0;
+  Bit32u apic_reg = addr & 0xff0;
   Bit32u value = *data;
-  switch(addr) {
+  switch(apic_reg) {
     case 0x20: // local APIC id
       id = (value>>24) & APIC_ID_MASK;
       break;
@@ -423,12 +423,12 @@ void bx_local_apic_c::write_aligned(bx_phy_address addr, Bit32u *data)
       // current count for timer
     case 0x390:
       // all read-only registers should fall into this line
-      BX_INFO(("warning: write to read-only APIC register 0x%02x", addr));
+      BX_INFO(("warning: write to read-only APIC register 0x%x", apic_reg));
       break;
     default:
       shadow_error_status |= APIC_ERR_ILLEGAL_ADDR;
       // but for now I want to know about it in case I missed some.
-      BX_PANIC(("APIC register %08x not implemented", addr));
+      BX_PANIC(("APIC register %x not implemented", apic_reg));
   }
 }
 
@@ -481,7 +481,7 @@ void bx_local_apic_c::send_ipi(void)
 
 void bx_local_apic_c::write_spurious_interrupt_register(Bit32u value)
 {
-  BX_DEBUG(("write %08x to spurious interrupt register", value));
+  BX_DEBUG(("write of %08x to spurious interrupt register", value));
 
 #ifdef BX_IMPLEMENT_XAPIC
   spurious_vector = value & 0xff;
@@ -529,7 +529,7 @@ void bx_local_apic_c::startup_msg(Bit32u vector)
     cpu->gen_reg[BX_32BIT_REG_EIP].dword.erx = 0;
     cpu->load_seg_reg(&cpu->sregs[BX_SEG_REG_CS], vector*0x100);
     BX_INFO(("%s started up at %04X:%08X by APIC",
-       cpu->name, vector*0x100, cpu->gen_reg[BX_32BIT_REG_EIP].dword.erx));
+       cpu->name, vector*0x100, cpu->get_eip()));
   } else {
     BX_INFO(("%s started up by APIC, but was not halted at the time", cpu->name));
   }
@@ -538,11 +538,11 @@ void bx_local_apic_c::startup_msg(Bit32u vector)
 // APIC read: 4 byte read from 16-byte aligned APIC address
 void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
 {
-  BX_DEBUG(("%s: LAPIC read from address %08x", cpu->name, addr));
+  BX_DEBUG(("%s: LAPIC read from address 0x" FMT_PHY_ADDRX, cpu->name, addr));
   BX_ASSERT((addr & 0xf) == 0);
   *data = 0;  // default value for unimplemented registers
-  bx_phy_address addr2 = addr & 0xff0;
-  switch(addr2) {
+  bx_phy_address apic_reg = addr & 0xff0;
+  switch(apic_reg) {
   case 0x20: // local APIC id
     *data = (id) << 24; break;
   case 0x30: // local APIC version
@@ -577,7 +577,7 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
   case 0x140: case 0x150:
   case 0x160: case 0x170:
     {
-      unsigned index = (addr2 - 0x100) << 1;
+      unsigned index = (apic_reg - 0x100) << 1;
       Bit32u value = 0, mask = 1;
       for(int i=0;i<32;i++) {
         if(isr[index+i]) value |= mask;
@@ -591,7 +591,7 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
   case 0x1c0: case 0x1d0:
   case 0x1e0: case 0x1f0:
     {
-      unsigned index = (addr2 - 0x180) << 1;
+      unsigned index = (apic_reg - 0x180) << 1;
       Bit32u value = 0, mask = 1;
       for(int i=0;i<32;i++) {
         if(tmr[index+i]) value |= mask;
@@ -605,7 +605,7 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
   case 0x240: case 0x250:
   case 0x260: case 0x270:
     {
-      unsigned index = (addr2 - 0x200) << 1;
+      unsigned index = (apic_reg - 0x200) << 1;
       Bit32u value = 0, mask = 1;
       for(int i=0;i<32;i++) {
         if(irr[index+i]) value |= mask;
@@ -627,7 +627,7 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
   case 0x360: // LVT Lint1 Reg
   case 0x370: // LVT Error Reg
     {
-      int index = (addr2 - 0x320) >> 4;
+      int index = (apic_reg - 0x320) >> 4;
       *data = lvt[index];
       break;
     }
@@ -638,10 +638,8 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
     if(timer_active==0) {
       *data = timer_current;
     } else {
-      Bit64u delta64;
-      Bit32u delta32;
-      delta64 = (bx_pc_system.time_ticks() - ticksInitial) / timer_divide_factor;
-      delta32 = (Bit32u) delta64;
+      Bit64u delta64 = (bx_pc_system.time_ticks() - ticksInitial) / timer_divide_factor;
+      Bit32u delta32 = (Bit32u) delta64;
       if(delta32 > timer_initial)
         BX_PANIC(("APIC: R(curr timer count): delta < initial"));
       timer_current = timer_initial - delta32;
@@ -652,10 +650,10 @@ void bx_local_apic_c::read_aligned(bx_phy_address addr, Bit32u *data)
     *data = timer_divconf;
     break;
   default:
-    BX_INFO(("APIC register %08x not implemented", addr));
+    BX_INFO(("APIC register %08x not implemented", apic_reg));
   }
 
-  BX_DEBUG(("%s: read from APIC address %08x = %08x", cpu->name, addr, *data));
+  BX_DEBUG(("%s: read from APIC address 0x" FMT_PHY_ADDRX " = %08x", cpu->name, addr, *data));
 }
 
 int bx_local_apic_c::highest_priority_int(Bit8u *array)
diff --git a/bochs/cpu/cpu.cc b/bochs/cpu/cpu.cc
index 2df9d3ce4..0ef169037 100644
--- a/bochs/cpu/cpu.cc
+++ b/bochs/cpu/cpu.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: cpu.cc,v 1.227 2008-05-04 05:37:36 sshwarts Exp $
+// $Id: cpu.cc,v 1.228 2008-05-09 22:33:36 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -668,10 +668,10 @@ void BX_CPU_C::prefetch(void)
   // Sanity checks
   if (! BX_CPU_THIS_PTR eipFetchPtr) {
     if (pAddr >= BX_MEM(0)->get_memory_len()) {
-      BX_PANIC(("prefetch: running in bogus memory, pAddr=0x%08x", pAddr));
+      BX_PANIC(("prefetch: running in bogus memory, pAddr=0x" FMT_PHY_ADDRX, pAddr));
     }
     else {
-      BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x%08x", pAddr));
+      BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x" FMT_PHY_ADDRX, pAddr));
     }
   }
 
diff --git a/bochs/cpu/paging.cc b/bochs/cpu/paging.cc
index 611ed0275..6d5a66a5c 100644
--- a/bochs/cpu/paging.cc
+++ b/bochs/cpu/paging.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: paging.cc,v 1.126 2008-05-02 22:47:07 sshwarts Exp $
+// $Id: paging.cc,v 1.127 2008-05-09 22:33:36 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -449,8 +449,8 @@ BX_CPU_C::pagingCR4Changed(Bit32u oldCR4, Bit32u newCR4)
 BX_CPU_C::CR3_change(bx_phy_address value)
 {
   if (bx_dbg.paging) {
-    BX_INFO(("CR3_change(): flush TLB cache"));
-    BX_INFO(("Page Directory Base %08x", (unsigned) value));
+    BX_DEBUG(("CR3_change(): flush TLB cache"));
+    BX_DEBUG(("Page Directory Base: 0x" FMT_PHY_ADDRX, value));
   }
 
   // flush TLB even if value does not change
@@ -657,11 +657,7 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned curr_pl, un
     // generate an exception if one is warranted.
   }
 
-#if BX_SUPPORT_X86_64
-  BX_DEBUG(("page walk for address 0x%08x:%08x", GET32H(laddr), GET32L(laddr)));
-#else
-  BX_DEBUG(("page walk for address 0x%08x", laddr));
-#endif
+  BX_DEBUG(("page walk for address 0x" FMT_LIN_ADDRX, laddr));
 
   InstrTLB_Increment(tlbMisses);
 
diff --git a/bochs/cpu/proc_ctrl.cc b/bochs/cpu/proc_ctrl.cc
index b6b9493e8..a220d19e1 100644
--- a/bochs/cpu/proc_ctrl.cc
+++ b/bochs/cpu/proc_ctrl.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: proc_ctrl.cc,v 1.226 2008-05-09 08:28:00 sshwarts Exp $
+// $Id: proc_ctrl.cc,v 1.227 2008-05-09 22:33:36 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -618,11 +618,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
       SetCR0(val_32);
       break;
     case 2: /* CR2 */
-      BX_DEBUG(("MOV_CdRd:CR2 = %08x", (unsigned) val_32));
+      BX_DEBUG(("MOV_CdRd:CR2 = %08x", val_32));
       BX_CPU_THIS_PTR cr2 = val_32;
       break;
     case 3: // CR3
-      BX_DEBUG(("MOV_CdRd:CR3 = %08x", (unsigned) val_32));
+      BX_DEBUG(("MOV_CdRd:CR3 = %08x", val_32));
       // Reserved bits take on value of MOV instruction
       CR3_change(val_32);
       BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR3, val_32);
@@ -728,13 +728,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
       SetCR0((Bit32u) val_64);
       break;
     case 2: /* CR2 */
-      BX_DEBUG(("MOV_CqRq: write to CR2 of %08x:%08x",
-          (Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF)));
+      BX_DEBUG(("MOV_CqRq: write to CR2 of %08x:%08x", GET32H(val_64), GET32L(val_64)));
       BX_CPU_THIS_PTR cr2 = val_64;
       break;
     case 3: // CR3
-      BX_DEBUG(("MOV_CqRq: write to CR3 of %08x:%08x",
-          (Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF)));
+      BX_DEBUG(("MOV_CqRq: write to CR3 of %08x:%08x", GET32H(val_64), GET32L(val_64)));
       if (val_64 & BX_CONST64(0xffffffff00000000)) {
           BX_PANIC(("CR3 write: Only 32 bit physical address space is emulated !"));
       }
@@ -745,8 +743,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
     case 4: // CR4
       //  Protected mode: #GP(0) if attempt to write a 1 to
       //  any reserved bit of CR4
-      BX_DEBUG(("MOV_CqRq: write to CR4 of %08x:%08x",
-          (Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF)));
+      BX_DEBUG(("MOV_CqRq: write to CR4 of %08x:%08x", GET32H(val_64), GET32L(val_64)));
       if (! SetCR4(val_64))
         exception(BX_GP_EXCEPTION, 0, 0);
       break;
@@ -2023,7 +2020,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MWAIT(bxInstruction_c *i)
   bx_pc_system.invlpg(BX_CPU_THIS_PTR monitor.monitor_begin);
   if ((BX_CPU_THIS_PTR monitor.monitor_end & ~0xfff) != (BX_CPU_THIS_PTR monitor.monitor_begin & ~0xfff))
     bx_pc_system.invlpg(BX_CPU_THIS_PTR monitor.monitor_end);
-  BX_DEBUG(("MWAIT for phys_addr=%08x", BX_CPU_THIS_PTR monitor.monitor_begin));
+  BX_DEBUG(("MWAIT for phys_addr=" FMT_PHY_ADDRX, BX_CPU_THIS_PTR monitor.monitor_begin));
   BX_MEM(0)->set_monitor(BX_CPU_THIS_PTR bx_cpuid);
 
   // stops instruction execution and places the processor in a optimized
diff --git a/bochs/cpu/tasking.cc b/bochs/cpu/tasking.cc
index 0451ce636..661937e14 100644
--- a/bochs/cpu/tasking.cc
+++ b/bochs/cpu/tasking.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: tasking.cc,v 1.57 2008-04-28 18:14:50 sshwarts Exp $
+// $Id: tasking.cc,v 1.58 2008-05-09 22:33:36 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -421,7 +421,7 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
     // change CR3 only if it actually modified
     if (newCR3 != BX_CPU_THIS_PTR cr3) {
       CR3_change(newCR3); // Tell paging unit about new cr3 value
-      BX_DEBUG (("task_switch changing CR3 to 0x%08x", newCR3));
+      BX_DEBUG (("task_switch changing CR3 to 0x" FMT_PHY_ADDRX, newCR3));
       BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_TASKSWITCH, newCR3);
     }
   }
diff --git a/bochs/memory/memory.cc b/bochs/memory/memory.cc
index 78509a7c7..11202fbc8 100644
--- a/bochs/memory/memory.cc
+++ b/bochs/memory/memory.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: memory.cc,v 1.67 2008-05-02 23:18:51 sshwarts Exp $
+// $Id: memory.cc,v 1.68 2008-05-09 22:33:37 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -52,7 +52,7 @@ void BX_MEM_C::writePhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned le
 
   // Note: accesses should always be contained within a single page now
   if ((addr>>12) != ((addr+len-1)>>12)) {
-    BX_PANIC(("writePhysicalPage: cross page access at address 0x%08x, len=%d", addr, len));
+    BX_PANIC(("writePhysicalPage: cross page access at address 0x" FMT_PHY_ADDRX ", len=%d", addr, len));
   }
 
 #if BX_SUPPORT_MONITOR_MWAIT
@@ -185,13 +185,13 @@ mem_write:
       {
         switch (DEV_pci_wr_memtype(a20addr)) {
           case 0x1:   // Writes to ShadowRAM
-            BX_DEBUG(("Writing to ShadowRAM: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
+            BX_DEBUG(("Writing to ShadowRAM: address 0x" FMT_PHY_ADDRX ", data %02x", a20addr, *data_ptr));
             *(BX_MEM_THIS get_vector(a20addr)) = *data_ptr;
             BX_DBG_DIRTY_PAGE(a20addr >> 12);
             break;
 
           case 0x0:   // Writes to ROM, Inhibit
-            BX_DEBUG(("Write to ROM ignored: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
+            BX_DEBUG(("Write to ROM ignored: address 0x" FMT_PHY_ADDRX ", data %02x", a20addr, *data_ptr));
             break;
 
           default:
@@ -212,7 +212,7 @@ inc_one:
   }
   else {
     // access outside limits of physical memory, ignore
-    BX_DEBUG(("Write outside the limits of physical memory (0x%08x) (ignore)", a20addr));
+    BX_DEBUG(("Write outside the limits of physical memory (0x"FMT_PHY_ADDRX") (ignore)", a20addr));
   }
 }
 
@@ -224,7 +224,7 @@ void BX_MEM_C::readPhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned len
 
   // Note: accesses should always be contained within a single page now
   if ((addr>>12) != ((addr+len-1)>>12)) {
-    BX_PANIC(("readPhysicalPage: cross page access at address 0x%08x, len=%d", addr, len));
+    BX_PANIC(("readPhysicalPage: cross page access at address 0x" FMT_PHY_ADDRX ", len=%d", addr, len));
   }
 
   if (cpu != NULL) {
diff --git a/bochs/memory/misc_mem.cc b/bochs/memory/misc_mem.cc
index 53440cbfb..9774c1e42 100644
--- a/bochs/memory/misc_mem.cc
+++ b/bochs/memory/misc_mem.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: misc_mem.cc,v 1.113 2008-05-01 20:28:36 sshwarts Exp $
+// $Id: misc_mem.cc,v 1.114 2008-05-09 22:33:37 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2002  MandrakeSoft S.A.
@@ -76,7 +76,7 @@ void BX_MEM_C::init_memory(Bit32u memsize)
 {
   unsigned idx;
 
-  BX_DEBUG(("Init $Id: misc_mem.cc,v 1.113 2008-05-01 20:28:36 sshwarts Exp $"));
+  BX_DEBUG(("Init $Id: misc_mem.cc,v 1.114 2008-05-09 22:33:37 sshwarts Exp $"));
 
   if (BX_MEM_THIS actual_vector != NULL) {
     BX_INFO (("freeing existing memory vector"));
@@ -637,7 +637,7 @@ BX_MEM_C::registerMemoryHandlers(void *param, memory_handler_t read_handler,
     return 0;
   if (!read_handler || !write_handler)
     return 0;
-  BX_INFO(("Register memory access handlers: %08x-%08x", begin_addr, end_addr));
+  BX_INFO(("Register memory access handlers: 0x" FMT_PHY_ADDRX " - 0x" FMT_PHY_ADDRX, begin_addr, end_addr));
   for (unsigned page_idx = begin_addr >> 20; page_idx <= end_addr >> 20; page_idx++) {
     struct memory_handler_struct *memory_handler = new struct memory_handler_struct;
     memory_handler->next = BX_MEM_THIS memory_handlers[page_idx];
@@ -656,7 +656,7 @@ BX_MEM_C::unregisterMemoryHandlers(memory_handler_t read_handler, memory_handler
 		bx_phy_address begin_addr, bx_phy_address end_addr)
 {
   bx_bool ret = 1;
-  BX_INFO(("Memory access handlers unregistered: %08x-%08x", begin_addr, end_addr));
+  BX_INFO(("Memory access handlers unregistered: 0x" FMT_PHY_ADDRX " - 0x" FMT_PHY_ADDRX, begin_addr, end_addr));
   for (unsigned page_idx = begin_addr >> 20; page_idx <= end_addr >> 20; page_idx++) {
     struct memory_handler_struct *memory_handler = BX_MEM_THIS memory_handlers[page_idx];
     struct memory_handler_struct *prev = NULL;