Stanislav Shwartsman
9f18573740
Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only)
2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
1e1c893041
introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it
2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
5e6955c5e7
Major rewrite of memory access methods to avoid massive code duplication and enable inlining of memory access methods
2015-01-25 20:55:10 +00:00
Stanislav Shwartsman
29efae3be3
adjust (c) in several files
2014-08-31 20:05:25 +00:00
Stanislav Shwartsman
5eb781e45f
cleanup after cpu features interface rework
2014-08-31 19:22:41 +00:00
Stanislav Shwartsman
be368f54d1
remove redundant type conversions
2014-03-23 20:01:58 +00:00
Stanislav Shwartsman
79456eb7e1
Implemented VPCMP* AVX512 instructions
...
Implemented VMOVNTPS/PD/DQ AVX512 instructions
Implemented VMOVNTDQA AVX512 instruction
Bugfixes for AVX-512
2013-12-02 18:05:18 +00:00
Stanislav Shwartsman
2b83146ae2
more avx-512 instructions implemented
2013-12-01 19:39:18 +00:00
Stanislav Shwartsman
fd383435f0
- Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon).
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The code already knows to disasm most of the opcodes with their operands.
- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance
- Minimize amount of opcode forms in ia_opcodes.h again.
For example Udq means the same as Wdq but with no memory form.
2013-09-30 19:01:42 +00:00
Stanislav Shwartsman
ff79cbd596
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
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The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.
Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
aa25c1db6a
name convention change - search and replace
2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
1cebe5f83d
rellback part of commit with xmm register access interface changes - doesn't work for big endian hosts
2013-09-16 19:10:42 +00:00
Stanislav Shwartsman
0cb0acc30f
added evex decode tables - next step to populate them :)
2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
0fd4e3450c
update (c) for few files
2013-09-05 18:40:14 +00:00
Stanislav Shwartsman
5d61c19b0b
evex support - step2
2013-08-27 20:47:24 +00:00
Stanislav Shwartsman
701d88388e
fixed FCS/FDS deprecation
2013-08-22 20:21:36 +00:00
Stanislav Shwartsman
c7698a5589
implemented fcs/fds deprecation. added haswell to cpudb.h as well
2013-06-20 20:12:53 +00:00
Stanislav Shwartsman
182ad65ea3
changes in avx emulation code
2012-12-09 16:42:48 +00:00
Stanislav Shwartsman
cc694377b9
Standartization of Bochs instruction handlers.
...
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.
Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code
Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)
Huge patch. Almost all source files wre modified.
2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
48ae41a2fd
fixed MASKMOVDQU SSE instruction to match hardware
2012-06-23 16:25:52 +00:00
Stanislav Shwartsman
1f14c171ed
rename some SSE handlers
2012-02-28 18:53:58 +00:00
Stanislav Shwartsman
d4541f1a88
removed dedicated handler for MOVNTI - can be replaced with existing handlers
2012-02-27 15:50:43 +00:00
Stanislav Shwartsman
44241a1e56
- Added support for AVX and AVX2 instructions emulation, to enable configure
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with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
b3898f4bec
small optimization for PALIGNR instruction
2011-08-25 19:29:33 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
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Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
08ba847ce4
fix bug inserted with prev commit + cleanup
2011-06-28 16:04:40 +00:00
Stanislav Shwartsman
2f582db722
compile less stuff for cpu-level=5
2011-06-26 19:15:30 +00:00
Stanislav Shwartsman
31be835056
bugfix + rename function
2011-06-14 19:56:28 +00:00
Stanislav Shwartsman
9fbf7d2f15
small cleanups
2011-05-04 05:53:17 +00:00
Stanislav Shwartsman
d440a5eda0
avx bug fix
2011-04-29 23:06:50 +00:00
Stanislav Shwartsman
c44f82f4ac
small cleanup
2011-04-25 20:26:22 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
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many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
faa8ee63a5
fixes to sse_move.cc
2011-02-11 10:08:42 +00:00
Stanislav Shwartsman
8c5c078b13
optimize sse and mmx code
2011-01-16 20:42:28 +00:00
Stanislav Shwartsman
45f0c72385
remove duplicated instr
2011-01-15 15:17:28 +00:00
Stanislav Shwartsman
a1bc92a46b
split more SSE opcodes
2011-01-08 11:20:29 +00:00
Stanislav Shwartsman
2946d0ac26
split more SSE ops
2010-12-30 21:45:39 +00:00
Stanislav Shwartsman
1bd512e98d
split more SSE ops, optimizations in MMX code
2010-12-25 17:04:36 +00:00
Stanislav Shwartsman
c005444d5b
split more SSE opcodes
2010-12-25 07:59:15 +00:00
Stanislav Shwartsman
040a8e1a3a
split bunch of SSE opcodes
2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
43600f3756
complete rework of SSE code
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next step - split all SSE opcodes by ModC0
2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
f2355a8249
Fixed FXSAVE/FXRSTOR exceptions order
2010-12-19 21:07:46 +00:00
Stanislav Shwartsman
48d94d6dc3
optimization
2010-12-18 11:58:16 +00:00
Stanislav Shwartsman
49c85b07f6
Fixed address size wrap
2010-10-18 22:19:45 +00:00
Stanislav Shwartsman
6d089dd238
changed CPUID constants to defines
2010-10-07 16:39:31 +00:00
Stanislav Shwartsman
8308a47168
trying to get rid of b1() in instruction class
2010-09-24 21:15:16 +00:00
Stanislav Shwartsman
41ddb26c6f
Fixed save/restore of x87 regs
2010-07-01 20:00:33 +00:00
Stanislav Shwartsman
689ecc57dd
split 2 more SSE opcodes
2010-04-08 17:35:32 +00:00
Stanislav Shwartsman
d39d485ece
changes variable name to better one
2010-04-03 05:59:07 +00:00
