mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
7,105 Commits 11 Branches 185 Tags 48 MiB
6714f3f8c1
Commit Graph

260 Commits

Author SHA1 Message Date
Stanislav Shwartsman
a9c77eb75d Try to optimize individual instructions after fetchdecode 2008-09-16 19:20:03 +00:00
Stanislav Shwartsman
23933d731c Remove 4G limit optimization that didn't work quite well 2008-09-08 20:47:33 +00:00
Stanislav Shwartsman
f5ba90da55 Misaligned check small optimization 2008-09-08 15:45:57 +00:00
Stanislav Shwartsman
79eb5efffa - Preliminary implementation of X86 IO breakpoints 2008-08-30 08:14:46 +00:00
Stanislav Shwartsman
db8445abde Allow 8b BP in 32bit mode as well 2008-08-29 22:14:02 +00:00
Stanislav Shwartsman
991ae348cb Clean invalidate_prefetch_q when not needed 2008-08-23 13:55:37 +00:00
Stanislav Shwartsman
460d91fc8c Added missed #GP fault when writing invalid memtype to MTRR/PAT 2008-08-15 10:59:31 +00:00
Stanislav Shwartsman
dcb82ec4bf Optimize TLB flush methods 2008-08-13 21:51:54 +00:00
Stanislav Shwartsman
24e0b53720 This more ellegant way to have debug info for BxError and not lose any performace 2008-08-09 19:18:09 +00:00
Stanislav Shwartsman
5dd02b26e3 Make even more efficient RmAddr calculation - good optimizing compiler could make more efficient code than it was before 2008-08-08 09:22:49 +00:00
Stanislav Shwartsman
6398ebb1d4 First step of access bits cleanup and optimization - no perf gain yet 2008-08-03 19:53:09 +00:00
Stanislav Shwartsman
924c87e451 Delete unused code 2008-07-13 15:36:57 +00:00
Stanislav Shwartsman
709d74728d Call #UD exception directly instead of UndefinedOpcode function - for future use 2008-07-13 15:35:10 +00:00
Stanislav Shwartsman
e9ec4fda48 Some chnages for future use 2008-07-13 10:44:34 +00:00
Stanislav Shwartsman
65275ffc02 Remove repeat speedups from 16-bit address size methods - they not gonna speed up anyway because of segment limit issue 2008-06-25 10:34:21 +00:00
Stanislav Shwartsman
c1f308d80d Push error code if segment violation occurs when pushing arguments into a new stack 2008-06-25 02:28:31 +00:00
Stanislav Shwartsman
b65816a92d Fixed problem in my morning checkin + some more changes 2008-06-23 15:58:22 +00:00
Stanislav Shwartsman
a6fda9a971 Instrumentation code updated, some PANIC messages fixed 2008-06-23 02:56:31 +00:00
Stanislav Shwartsman
fc6671a67b Commented out assertion which doesn't work 2008-06-16 04:49:19 +00:00
Stanislav Shwartsman
9d1bc903d8 Fixed typo in MTRR, added assertions 2008-06-15 20:41:34 +00:00
Stanislav Shwartsman
a0e66d0e4c fixed variable name 2008-06-14 16:55:45 +00:00
Stanislav Shwartsman
92568f7525 Faster 32-bit emulation wwith 64-bit enabled mode. 
~10% speedup byu optimization of 32-bit mem access
 2008-06-12 19:14:40 +00:00
Stanislav Shwartsman
3d3dba7804 - Implemented GD bit in DR7 register 2008-06-02 19:50:40 +00:00
Stanislav Shwartsman
b7480b3e6f - Fixed x86 data breakpoint match when breakpoint length is 8 bytes 
- FIxed x86 data breakpoint in paging disabled mode
 2008-06-02 18:41:08 +00:00
Stanislav Shwartsman
d2ba79abdd Removed PANIC in DqRq function 2008-05-31 21:17:02 +00:00
Stanislav Shwartsman
764756d74a Handle reserved bits of CR8 2008-05-31 09:26:28 +00:00
Stanislav Shwartsman
d295371450 - Correctly handle segment a byte in BIG real mode 2008-05-26 21:46:39 +00:00
Stanislav Shwartsman
3619c0f6b4 Some changes to make x86-debugger feature working back 2008-05-23 17:49:46 +00:00
Stanislav Shwartsman
8118ba1a67 Fixed debug extensions exception priority 2008-05-19 19:59:29 +00:00
Stanislav Shwartsman
bef3450baa Fixes to 64-bit mode 2008-05-11 20:46:11 +00:00
Stanislav Shwartsman
4a76bd2169 Fixed setting of reserved bits in CR3 register 2008-05-11 19:36:06 +00:00
Stanislav Shwartsman
ec1ff39a5f Splitted memory access methods for 32 and 64-bit code. 
The 64-bit code got >10% speedup, the 32-bit code also got about 2% because laddr cacluation optimization
 2008-05-10 18:10:53 +00:00
Stanislav Shwartsman
3634c6f892 Compress FPU tag word 2008-05-10 13:34:47 +00:00
Stanislav Shwartsman
6ebae41ad7 print physcial address with special format - preparations for 64-bit physical address emu 2008-05-09 22:33:37 +00:00
Stanislav Shwartsman
80c9b5fcbe Compilation error fixed 2008-05-09 08:28:00 +00:00
Stanislav Shwartsman
eedf26627f Fixes in CMPXHG8B instruction - slight speedup and correct #AC check 2008-05-05 21:48:07 +00:00
Stanislav Shwartsman
64a80c8a2d - Added canonical check for SYSENTER MSRs in WRMSR 
- Fixed LLDT and LTR instructions in 64-bit mode
- Fixed error code for not 64-bit CS in interrupt from long mode
 2008-05-04 21:25:16 +00:00
Stanislav Shwartsman
50c9674d2e Small optimization in memory access functions 2008-05-03 17:33:30 +00:00
Stanislav Shwartsman
06c6ac0060 - Fixed effective address wrap in 64-bit mode with 32-bit address size 
- Fixed SMSW instruction in 32-bit and 64-bit modes
 2008-04-28 18:18:08 +00:00
Stanislav Shwartsman
67e534832b Remove from CPU reference to MEM object - it is only one and could be static 2008-04-27 19:49:02 +00:00
Stanislav Shwartsman
9047c9be96 Support for reserved bits checking in paging 
Check for page is in DTLB before invalidating by INVLPG
 2008-04-25 20:08:23 +00:00
Stanislav Shwartsman
a647c7e551 Check for old TSS limits in task switching logic 
MSR_GSKERNELBASE should be canonical - added WRMSR check
 2008-04-25 11:39:51 +00:00
Stanislav Shwartsman
24f1507fa9 - sysenter/exit should be supported in v8086 mode as well 
- fixed missed CS.LIMIT check in all far calls/jmps in real/v8086 mode
 2008-04-20 21:44:13 +00:00
Stanislav Shwartsman
280617288c Mode change in SYSENTER/EXIT/CALL/RET could happen only when already in long mode 2008-04-20 18:17:14 +00:00
Stanislav Shwartsman
a91ef4e31b Ignore CS.L bit when EFER.LMA is not set 
Add potentially missed CPU mode change in SYSCALL/RET/ENTER/EXIT
 2008-04-20 18:10:32 +00:00
Stanislav Shwartsman
d9bf2b8453 Small emulation speed optimization 2008-04-19 22:29:44 +00:00
Stanislav Shwartsman
15e9dca062 - support 64-bit write to MSR_TSC using WRMSR instruction 
- fixed save/restore param type for async_event
- fixed setting of reserved bits in upper part of CR4 in 64-bit mode
 2008-04-18 18:32:40 +00:00
Stanislav Shwartsman
892fa99c6f - prefetch hint should be NOP when use in register mode 
- #GP when trying to set reserved bits of CR4_HI in 64-bit mode
- #GP when trying to set reserved bits of EFER MSR
- clear upper part of RSI/RDI when executing rep instructions with 32-bit asize
  even if no repeat iterations were executed (because of RCX=0 for example)
- write SYSENTER_EIP_MSR and SYSENTER_ESP_MSR as 64-bit when x86_64 supported
- set MSR_FMASK reset value
- MSR_FMASK should be 32-bit only
- check for fetch permissions when doing ITLB lookup
- #GP when trying to write non-canonical address to MSR_CSTAR or MSR_LSTAR
- correct repeat instructions timing
- mark TSS busy in TR after it is loaded
 2008-04-16 16:44:06 +00:00
Stanislav Shwartsman
67f02bfa12 Add debugger callback 2008-04-15 21:29:18 +00:00
Stanislav Shwartsman
fab4042cad SYSENTER/SYSEXIT in long mode 2008-04-15 14:41:50 +00:00