Fixed debug extensions exception priority
This commit is contained in:
Stanislav Shwartsman
parent
e98b58651d
commit
8118ba1a67
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.231 2008-05-11 20:46:11 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.232 2008-05-19 19:59:29 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -219,6 +219,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CLFLUSH(bxInstruction_c *i)
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#if BX_CPU_LEVEL >= 3
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
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{
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#if BX_CPU_LEVEL >= 4
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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if ((i->nnn() & 0xE) == 4) {
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BX_ERROR(("MOV_DdRd: access to DR4/DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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}
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#endif
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if (!real_mode() && CPL!=0) {
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BX_ERROR(("MOV_DdRd: CPL!=0 not in real mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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@ -255,16 +264,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
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break;
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case 4: // DR4
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// access to DR4 causes #UD
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#if BX_CPU_LEVEL >= 4
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_DdRd: access to DR4 causes #UD"));
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UndefinedOpcode(i);
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}
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#endif
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// Fall through to DR6 case
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case 6: // DR6
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#if BX_CPU_LEVEL <= 4
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// On 386/486 bit12 is settable
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@ -278,16 +279,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DdRd(bxInstruction_c *i)
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break;
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case 5: // DR5
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// access to DR5 causes #UD
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#if BX_CPU_LEVEL >= 4
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_DdRd: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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#endif
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// Fall through to DR7 case
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case 7: // DR7
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// Note: 486+ ignore GE and LE flags. On the 386, exact
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// data breakpoint matching does not occur unless it is enabled
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@ -345,6 +338,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
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{
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Bit32u val_32;
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#if BX_CPU_LEVEL >= 4
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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if ((i->nnn() & 0xE) == 4) {
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BX_ERROR(("MOV_RdDd: access to DR4/DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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}
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#endif
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if (!real_mode() && CPL!=0) {
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BX_ERROR(("MOV_RdDd: CPL!=0 not in real mode"));
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exception(BX_GP_EXCEPTION, 0, 0);
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@ -371,31 +373,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
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break;
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case 4: // DR4
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// DR4 aliased to DR6 by default. With Debug Extensions ON,
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// access to DR4 causes #UD
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#if BX_CPU_LEVEL >= 4
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_RdDd: access to DR4 causes #UD"));
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UndefinedOpcode(i);
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}
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#endif
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// Fall through to DR6 case
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case 6: // DR6
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val_32 = BX_CPU_THIS_PTR dr6;
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break;
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case 5: // DR5
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// DR5 aliased to DR7 by default. With Debug Extensions ON,
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// access to DR5 causes #UD
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#if BX_CPU_LEVEL >= 4
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_RdDd: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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#endif
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// Fall through to DR7 case
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case 7: // DR7
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val_32 = BX_CPU_THIS_PTR dr7;
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break;
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@ -411,14 +397,19 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RdDd(bxInstruction_c *i)
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#if BX_SUPPORT_X86_64
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
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{
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BX_ASSERT(protected_mode());
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/* NOTES:
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* 64bit operands always used
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* r/m field specifies general register
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* reg field specifies which special register
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*/
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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if ((i->nnn() & 0xE) == 4) {
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BX_ERROR(("MOV_DqRq: access to DR4/DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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}
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/* #GP(0) if CPL is not 0 */
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if (CPL != 0) {
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BX_ERROR(("MOV_DqRq: #GP(0) if CPL is not 0"));
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@ -450,14 +441,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
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break;
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case 4: // DR4
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// DR4 aliased to DR6 by default. With Debug Extensions ON,
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// access to DR4 causes #UD
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_DqRq: access to DR4 causes #UD"));
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UndefinedOpcode(i);
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}
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// Fall through to DR6 case
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case 6: // DR6
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// On Pentium+, bit12 is always zero
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BX_CPU_THIS_PTR dr6 = (BX_CPU_THIS_PTR dr6 & 0xffff0ff0) |
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@ -465,14 +450,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_DqRq(bxInstruction_c *i)
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break;
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case 5: // DR5
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// DR5 aliased to DR7 by default. With Debug Extensions ON,
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// access to DR5 causes #UD
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_DqRq: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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// Fall through to DR7 case
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case 7: // DR7
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// Note: 486+ ignore GE and LE flags. On the 386, exact
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// data breakpoint matching does not occur unless it is enabled
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@ -527,7 +506,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
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{
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Bit64u val_64;
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BX_ASSERT(protected_mode());
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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if ((i->nnn() & 0xE) == 4) {
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BX_ERROR(("MOV_DqRq: access to DR4/DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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}
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/* #GP(0) if CPL is not 0 */
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if (CPL != 0) {
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@ -556,27 +540,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_RqDq(bxInstruction_c *i)
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break;
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case 4: // DR4
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// DR4 aliased to DR6 by default. With Debug Extensions on,
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// DR4 aliased to DR6 by default. With Debug Extensions ON,
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// access to DR4 causes #UD
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_RqDq: access to DR4 causes #UD"));
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UndefinedOpcode(i);
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}
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// Fall through to DR6 case
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case 6: // DR6
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val_64 = BX_CPU_THIS_PTR dr6;
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break;
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case 5: // DR5
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// DR5 aliased to DR7 by default. With Debug Extensions on,
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// DR5 aliased to DR7 by default. With Debug Extensions ON,
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// access to DR5 causes #UD
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if (BX_CPU_THIS_PTR cr4.get_DE()) {
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// Debug extensions CR4.DE is ON
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BX_INFO(("MOV_RqDq: access to DR5 causes #UD"));
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UndefinedOpcode(i);
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}
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// Fall through to DR7 case
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case 7: // DR7
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val_64 = BX_CPU_THIS_PTR dr7;
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break;
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@ -850,7 +822,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LMSW_Ew(bxInstruction_c *i)
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if (BX_CPU_THIS_PTR cr0.get_PE())
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msw |= 0x0001; // adjust PE bit to current value of 1
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msw &= 0x000f; // LMSW only affects last 4 flags
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msw &= 0xf; // LMSW only affects last 4 flags
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cr0 = (BX_CPU_THIS_PTR cr0.getRegister() & 0xfffffff0) | msw;
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SetCR0(cr0);
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}
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