Small optimization in memory access functions
This commit is contained in:
parent
001ad1c736
commit
50c9674d2e
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: access.cc,v 1.102 2008-05-01 05:11:19 sshwarts Exp $
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// $Id: access.cc,v 1.103 2008-05-03 17:33:30 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -55,7 +55,7 @@ BX_CPU_C::write_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsigne
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exception(int_number(seg), 0, 0);
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}
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// Mark cache as being OK type for succeeding reads/writes
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccess4G;
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccessROK4G | SegAccessWOK4G;
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return;
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}
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#endif
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@ -98,7 +98,7 @@ BX_CPU_C::write_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsigne
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seg->cache.valid |= SegAccessROK | SegAccessWOK;
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if (seg->cache.u.segment.limit_scaled == 0xffffffff)
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seg->cache.valid |= SegAccess4G;
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seg->cache.valid |= SegAccessROK4G | SegAccessWOK4G;;
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}
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break;
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@ -114,7 +114,7 @@ BX_CPU_C::write_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsigne
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exception(int_number(seg), 0, 0);
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}
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if (seg->cache.u.segment.limit_scaled == 0)
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seg->cache.valid |= SegAccess4G | SegAccessROK | SegAccessWOK;
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccessROK4G | SegAccessWOK4G;
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break;
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}
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@ -138,7 +138,7 @@ BX_CPU_C::write_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsigne
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seg->cache.valid |= SegAccessROK | SegAccessWOK;
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if (seg->cache.u.segment.limit_scaled == 0xffffffff)
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seg->cache.valid |= SegAccess4G;
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seg->cache.valid |= SegAccessROK4G | SegAccessWOK4G;
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}
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}
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}
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@ -156,7 +156,7 @@ BX_CPU_C::read_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsigned
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exception(int_number(seg), 0, 0);
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}
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// Mark cache as being OK type for succeeding reads/writes
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccess4G;
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccessROK4G | SegAccessWOK4G;
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return;
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}
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#endif
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@ -187,7 +187,7 @@ BX_CPU_C::read_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsigned
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// write checks; similar code.
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seg->cache.valid |= SegAccessROK;
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if (seg->cache.u.segment.limit_scaled == 0xffffffff)
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seg->cache.valid |= SegAccess4G;
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seg->cache.valid |= SegAccessROK4G;
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}
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break;
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@ -204,7 +204,7 @@ BX_CPU_C::read_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsigned
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exception(int_number(seg), 0, 0);
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}
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if (seg->cache.u.segment.limit_scaled == 0)
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seg->cache.valid |= SegAccess4G | SegAccessROK;
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seg->cache.valid |= SegAccessROK | SegAccessROK4G;
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break;
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case 8: case 9: /* execute only */
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@ -233,7 +233,7 @@ BX_CPU_C::read_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsigned
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seg->cache.valid |= SegAccessROK | SegAccessWOK;
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if (seg->cache.u.segment.limit_scaled == 0xffffffff)
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seg->cache.valid |= SegAccess4G;
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seg->cache.valid |= SegAccessROK4G | SegAccessWOK4G;
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}
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}
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}
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@ -251,7 +251,7 @@ BX_CPU_C::execute_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsig
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exception(int_number(seg), 0, 0);
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}
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// Mark cache as being OK type for succeeding reads/writes
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccess4G;
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seg->cache.valid |= SegAccessROK | SegAccessWOK | SegAccessROK4G | SegAccessWOK4G;
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return;
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}
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#endif
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@ -282,7 +282,7 @@ BX_CPU_C::execute_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsig
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// write checks; similar code.
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seg->cache.valid |= SegAccessROK;
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if (seg->cache.u.segment.limit_scaled == 0xffffffff)
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seg->cache.valid |= SegAccess4G;
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seg->cache.valid |= SegAccessROK4G;
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}
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break;
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@ -309,7 +309,7 @@ BX_CPU_C::execute_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsig
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exception(int_number(seg), 0, 0);
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}
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if (seg->cache.u.segment.limit_scaled == 0)
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seg->cache.valid |= SegAccess4G | SegAccessROK;
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seg->cache.valid |= SegAccessROK | SegAccessROK4G;
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break;
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}
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return;
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@ -332,7 +332,7 @@ BX_CPU_C::execute_virtual_checks(bx_segment_reg_t *seg, bx_address offset, unsig
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seg->cache.valid |= SegAccessROK | SegAccessWOK;
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if (seg->cache.u.segment.limit_scaled == 0xffffffff)
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seg->cache.valid |= SegAccess4G;
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seg->cache.valid |= SegAccessROK4G | SegAccessWOK4G;
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}
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}
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}
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@ -471,7 +471,7 @@ BX_CPU_C::write_virtual_byte(unsigned s, bx_address offset, Bit8u data)
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 1, BX_WRITE);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -521,7 +521,7 @@ BX_CPU_C::write_virtual_word(unsigned s, bx_address offset, Bit16u data)
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 2, BX_WRITE);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -579,7 +579,7 @@ BX_CPU_C::write_virtual_dword(unsigned s, bx_address offset, Bit32u data)
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 4, BX_WRITE);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -637,7 +637,7 @@ BX_CPU_C::write_virtual_qword(unsigned s, bx_address offset, Bit64u data)
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bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s];
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 8, BX_WRITE);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -696,7 +696,7 @@ BX_CPU_C::read_virtual_byte(unsigned s, bx_address offset)
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Bit8u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 1, BX_READ);
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if ((seg->cache.valid & SegAccessROK4G) == SegAccessROK4G) {
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if (seg->cache.valid & SegAccessROK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -744,7 +744,7 @@ BX_CPU_C::read_virtual_word(unsigned s, bx_address offset)
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Bit16u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 2, BX_READ);
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if ((seg->cache.valid & SegAccessROK4G) == SegAccessROK4G) {
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if (seg->cache.valid & SegAccessROK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -800,7 +800,7 @@ BX_CPU_C::read_virtual_dword(unsigned s, bx_address offset)
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Bit32u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 4, BX_READ);
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if ((seg->cache.valid & SegAccessROK4G) == SegAccessROK4G) {
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if (seg->cache.valid & SegAccessROK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -856,7 +856,7 @@ BX_CPU_C::read_virtual_qword(unsigned s, bx_address offset)
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Bit64u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 8, BX_READ);
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if ((seg->cache.valid & SegAccessROK4G) == SegAccessROK4G) {
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if (seg->cache.valid & SegAccessROK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -917,7 +917,7 @@ BX_CPU_C::read_RMW_virtual_byte(unsigned s, bx_address offset)
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Bit8u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 1, BX_RW);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -971,7 +971,7 @@ BX_CPU_C::read_RMW_virtual_word(unsigned s, bx_address offset)
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Bit16u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 2, BX_RW);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -1031,7 +1031,7 @@ BX_CPU_C::read_RMW_virtual_dword(unsigned s, bx_address offset)
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Bit32u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 4, BX_RW);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -1091,7 +1091,7 @@ BX_CPU_C::read_RMW_virtual_qword(unsigned s, bx_address offset)
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Bit64u data;
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BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 8, BX_RW);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = BX_CPU_THIS_PTR get_laddr(s, offset);
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#if BX_SupportGuest2HostTLB
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@ -1411,7 +1411,7 @@ void BX_CPU_C::write_new_stack_word(bx_segment_reg_t *seg, bx_address offset, un
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = (Bit32u)(seg->cache.u.segment.base + offset);
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#if BX_SupportGuest2HostTLB
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@ -1463,7 +1463,7 @@ void BX_CPU_C::write_new_stack_dword(bx_segment_reg_t *seg, bx_address offset, u
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BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
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if ((seg->cache.valid & SegAccessWOK4G) == SegAccessWOK4G) {
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if (seg->cache.valid & SegAccessWOK4G) {
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accessOK:
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laddr = (Bit32u)(seg->cache.u.segment.base + offset);
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#if BX_SupportGuest2HostTLB
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: descriptor.h,v 1.21 2007-12-10 19:08:13 sshwarts Exp $
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// $Id: descriptor.h,v 1.22 2008-05-03 17:33:30 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2007 Stanislav Shwartsman
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@ -40,13 +40,11 @@ typedef struct { /* bx_selector_t */
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typedef struct
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{
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#define SegValidCache (0x1)
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#define SegAccessROK (0x2)
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#define SegAccessWOK (0x4)
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#define SegAccess4G (0x8)
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#define SegAccessROK4G (SegAccessROK|SegAccess4G)
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#define SegAccessWOK4G (SegAccessWOK|SegAccess4G)
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#define SegValidCache (0x01)
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#define SegAccessROK (0x02)
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#define SegAccessWOK (0x04)
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#define SegAccessROK4G (0x08)
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#define SegAccessWOK4G (0x10)
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unsigned valid; // Holds above values, Or'd together. Used to
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// hold only 0 or 1.
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: io.cc,v 1.58 2008-04-27 19:49:02 sshwarts Exp $
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// $Id: io.cc,v 1.59 2008-05-03 17:33:30 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -54,7 +54,7 @@ Bit32u BX_CPU_C::FastRepINSW(bxInstruction_c *i, bx_address dstOff, Bit16u port,
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unsigned count;
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bx_segment_reg_t *dstSegPtr = &BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES];
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if ((dstSegPtr->cache.valid & SegAccessWOK4G) != SegAccessWOK4G)
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if (!(dstSegPtr->cache.valid & SegAccessWOK4G))
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return 0;
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bx_address laddrDst = BX_CPU_THIS_PTR get_laddr(BX_SEG_REG_ES, dstOff);
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@ -138,7 +138,7 @@ Bit32u BX_CPU_C::FastRepOUTSW(bxInstruction_c *i, unsigned srcSeg, bx_address sr
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unsigned count;
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bx_segment_reg_t *srcSegPtr = &BX_CPU_THIS_PTR sregs[srcSeg];
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if ((srcSegPtr->cache.valid & SegAccessROK4G) != SegAccessROK4G)
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if (!(srcSegPtr->cache.valid & SegAccessROK4G))
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return 0;
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bx_address laddrSrc = BX_CPU_THIS_PTR get_laddr(srcSeg, srcOff);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.222 2008-04-28 18:18:08 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.223 2008-05-03 17:33:30 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -191,7 +191,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CLFLUSH(bxInstruction_c *i)
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BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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// check if we could access the memory segment
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if ((seg->cache.valid & SegAccessROK4G) != SegAccessROK4G)
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if (!(seg->cache.valid & SegAccessROK4G))
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{
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execute_virtual_checks(seg, RMAddr(i), 1);
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: string.cc,v 1.58 2008-04-27 19:49:02 sshwarts Exp $
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// $Id: string.cc,v 1.59 2008-05-03 17:33:30 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -50,11 +50,11 @@ Bit32u BX_CPU_C::FastRepMOVSB(bxInstruction_c *i, unsigned srcSeg, bx_address sr
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Bit8u *hostAddrSrc, *hostAddrDst;
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bx_segment_reg_t *srcSegPtr = &BX_CPU_THIS_PTR sregs[srcSeg];
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if ((srcSegPtr->cache.valid & SegAccessROK4G) != SegAccessROK4G)
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if (!(srcSegPtr->cache.valid & SegAccessROK4G))
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return 0;
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bx_segment_reg_t *dstSegPtr = &BX_CPU_THIS_PTR sregs[dstSeg];
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if ((dstSegPtr->cache.valid & SegAccessWOK4G) != SegAccessWOK4G)
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if (!(dstSegPtr->cache.valid & SegAccessWOK4G))
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return 0;
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laddrSrc = BX_CPU_THIS_PTR get_laddr(srcSeg, srcOff);
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@ -145,11 +145,11 @@ Bit32u BX_CPU_C::FastRepMOVSW(bxInstruction_c *i, unsigned srcSeg, bx_address sr
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Bit8u *hostAddrSrc, *hostAddrDst;
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bx_segment_reg_t *srcSegPtr = &BX_CPU_THIS_PTR sregs[srcSeg];
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if ((srcSegPtr->cache.valid & SegAccessROK4G) != SegAccessROK4G)
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if (!(srcSegPtr->cache.valid & SegAccessROK4G))
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return 0;
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bx_segment_reg_t *dstSegPtr = &BX_CPU_THIS_PTR sregs[dstSeg];
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if ((dstSegPtr->cache.valid & SegAccessWOK4G) != SegAccessWOK4G)
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if (!(dstSegPtr->cache.valid & SegAccessWOK4G))
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return 0;
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laddrSrc = BX_CPU_THIS_PTR get_laddr(srcSeg, srcOff);
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@ -243,11 +243,11 @@ Bit32u BX_CPU_C::FastRepMOVSD(bxInstruction_c *i, unsigned srcSeg, bx_address sr
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Bit8u *hostAddrSrc, *hostAddrDst;
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bx_segment_reg_t *srcSegPtr = &BX_CPU_THIS_PTR sregs[srcSeg];
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if ((srcSegPtr->cache.valid & SegAccessROK4G) != SegAccessROK4G)
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if (!(srcSegPtr->cache.valid & SegAccessROK4G))
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return 0;
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bx_segment_reg_t *dstSegPtr = &BX_CPU_THIS_PTR sregs[dstSeg];
|
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if ((dstSegPtr->cache.valid & SegAccessWOK4G) != SegAccessWOK4G)
|
||||
if (!(dstSegPtr->cache.valid & SegAccessWOK4G))
|
||||
return 0;
|
||||
|
||||
laddrSrc = BX_CPU_THIS_PTR get_laddr(srcSeg, srcOff);
|
||||
@ -473,7 +473,7 @@ Bit32u BX_CPU_C::FastRepSTOSD(bxInstruction_c *i, unsigned dstSeg, bx_address ds
|
||||
Bit8u *hostAddrDst;
|
||||
|
||||
bx_segment_reg_t *dstSegPtr = &BX_CPU_THIS_PTR sregs[dstSeg];
|
||||
if ((dstSegPtr->cache.valid & SegAccessWOK4G) != SegAccessWOK4G)
|
||||
if (!(dstSegPtr->cache.valid & SegAccessWOK4G))
|
||||
return 0;
|
||||
|
||||
laddrDst = BX_CPU_THIS_PTR get_laddr(dstSeg, dstOff);
|
||||
|
Loading…
Reference in New Issue
Block a user