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255 Commits

Author SHA1 Message Date
Stanislav Shwartsman
93146256f8 disasm updates 2019-02-08 16:28:51 +00:00
Stanislav Shwartsman
4c18ee784f disasm updates 2019-02-08 16:26:56 +00:00
Stanislav Shwartsman
9abd8ba8fa old legacy disasm: omit printing rep prefix if no repeatable opcode 2017-12-28 20:52:46 +00:00
Stanislav Shwartsman
9659641cbf distinguish between vzeroupper/vzeroall in old legacy disasm 2017-12-28 20:20:13 +00:00
Stanislav Shwartsman
4b7d7c9501 align UD opcodes with latest Intel SDM in old disasm 2017-12-17 18:55:03 +00:00
Stanislav Shwartsman
e0c3433f7f bugfix in old disasm 2017-12-16 19:34:14 +00:00
Stanislav Shwartsman
5dc5e01a12 disasm fixes and reorg of pinsr* opcodes 2017-12-16 18:34:20 +00:00
Stanislav Shwartsman
df877cc03d adjustments to old disasm done during validation of new disasm 2017-12-13 18:18:20 +00:00
Stanislav Shwartsman
2a55ba0a39 Merge set of debugger improvements by Doug Gale <doug16k> 
Here is his original comment:

I have made several improvements in the debugger.
I have fixed several issues with proper handling of 64-bit addresses, and added support for 64 bit symbols.
I also have added several symbol lookups.
 2017-08-22 21:03:58 +00:00
Stanislav Shwartsman
48a2bc2cbf change disasm memsize print 2017-05-26 11:21:56 +00:00
Stanislav Shwartsman
7a34f00f99 extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all 2016-06-12 21:23:48 +00:00
Stanislav Shwartsman
09e6ee3143 compile disasm module when x86-64 is not compiled in 2016-05-12 11:16:05 +00:00
Stanislav Shwartsman
793ceb0d8c fix massive code dupliction between disasm, debugger and cpu by introducing new cpu decoder.h header 2016-04-29 21:01:28 +00:00
Stanislav Shwartsman
adc143684b implemented Intel architecture extensions published in recently published SDM 058: 
! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
 2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
bcb36e81fa experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys 2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
18f07937d2 add new cpuid bit announced in sdm rev057 to disasm features list as well 2015-12-29 20:22:33 +00:00
Stanislav Shwartsman
080ceb8293 don't crash when running on 386 with no FPU model 2015-03-27 21:39:24 +00:00
Stanislav Shwartsman
987e2ad223 Added definitions from recently published Intel Architecture 
Instruction Set Extensions Programming Reference rev22.
Implemented CLWB instruction
 2014-11-01 13:12:24 +00:00
Stanislav Shwartsman
e2e6f5a62b Update CPUID defines after recently published 
Intel Architecture Instruction Set Extensions Programming Reference rev-021

Enable AVX-512 with all implemented extensions in generic CPUID when simd=AVX512 is supplied
implemented AVX512_IFMA532 instructions
implemented AVX512_VBMI instructions

still missing: VPMULTISHIFTQB - VBMI instruction (coming soon)
 2014-09-26 12:14:53 +00:00
Stanislav Shwartsman
9f57e70d5f Rewritten handling of supported CPUID features to be able to handle large amount of CPU extensions 
Now enable support for up to 128 CPU extensions and could easily extend it more
Also reduce memory footprint for bx_ia_opcodes.h arrays
 2014-08-31 18:39:18 +00:00
Stanislav Shwartsman
94864fb9bc Implement AVX512BW and AVX512DQ extensions published in recently published Intel Archtecture Extensions manual rev20. 
https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf

Most of the instructions are implemented, more on the way.

+ few bugfixes for legacy AVX-512 emulation

AVX-512: Fixed bug in VCMPPS masked instruction implementation with 512-bit data size
AVX-512: Fixed AVX-512 masked convert instructions with non-k0 mask (behaved as non masked versions)
AVX-512: Fixed missed #UD due to invalid EVEX prefix fields for several AVX-512 opcodes (VFIXUPIMMSS/SD, FMA)
 2014-07-18 11:14:25 +00:00
Stanislav Shwartsman
ab6230a9a8 Implemented XSAVEC instruction emulation and XINUSE optimization in the XSAVEOPT instruction 2014-03-17 20:29:44 +00:00
Stanislav Shwartsman
550e6bd307 moved (c) to year 2014 for few files 2014-02-06 17:06:25 +00:00
Stanislav Shwartsman
aea9ae1976 added definitions (CPUID bit, VMX fields and VMXEXIT reasons, etc) from recently published Intel SDM rev049 2014-02-06 17:05:20 +00:00
Stanislav Shwartsman
36ba25847f Implemented last missed AVX-512 unsigned convert instructions 
The only missed AVX-512 opcodes now are:

512.66.0F38.W0 13 VCVTPH2PS
512.66.0F3A.W0 1D VCVTPS2PH

512.66.0F38.WIG 21 VPMOVSXBD
512.66.0F38.WIG 22 VPMOVSXBQ
512.66.0F38.WIG 23 VPMOVSXWD
512.66.0F38.WIG 24 VPMOVSXWQ
512.66.0F38.W0  25 VPMOVSXDQ

512.66.0F38.WIG 31 VPMOVSZBD
512.66.0F38.WIG 32 VPMOVSZBQ
512.66.0F38.WIG 33 VPMOVSZWD
512.66.0F38.WIG 34 VPMOVSZWQ
512.66.0F38.W0  35 VPMOVSzDQ

512.66.0F38.W0 2C VSCALEFPS
512.66.0F38.W1 2C VSCALEFPD
NDS.LIG.66.0F38.W0 2D VSCALESS
NDS.LIG.66.0F38.W1 2D VSCALESD

512.66.0F38.W0 4C VRCP14PS
 512.66.0F38.W1 4C VRCP14PD
NDS.LIG.66.0F38.W0 4D VRCP14SS
 NDS.LIG.66.0F38.W1 4D VRCP14SD
512.66.0F38.W0 4E VRSQRT14PS
 512.66.0F38.W1 4E VRSQRT14PD
NDS.LIG.66.0F38.W0 4F VRSQRT14SS
 NDS.LIG.66.0F38.W1 4F VRSQRT14SD

NDS.512.66.0F3A.W0 03 VALIGND
NDS.512.66.0F3A.W1 03 VALIGNQ

512.66.0F3A.W0 08 VRNDSCALEPS
512.66.0F3A.W1 09 VRNDSCALEPD
NDS.LIG.66.0F3A.W1 0A VRNDSCALESS
NDS.LIG.66.0F3A.W1 0B VRNDSCALESD

512.66.0F3A.W0 19 VEXTRACTF32x4
512.66.0F3A.W1 1B VEXTRACTF64x4
512.66.0F3A.W0 39 VEXTRACTI32x4
512.66.0F3A.W1 3B VEXTRACTI64x4

512.66.0F3A.W0 26 VGETMANTPS
 512.66.0F3A.W1 26 VGETMANTPD
NDS.LIG.66.0F3A.W0 27 VGETMANTSS
 NDS.LIG.66.0F3A.W1 27 VGETMANTSD
 2014-01-28 12:57:38 +00:00
Stanislav Shwartsman
c3b666d4ed fixed zmm reg name in disasm 2013-11-29 20:49:20 +00:00
Stanislav Shwartsman
940c2a1c8e fixes for disasm 2013-10-15 17:19:18 +00:00
Stanislav Shwartsman
9fb7384e6b finish sse tables cleanup in disasm and fetchdecode 2013-10-11 20:09:51 +00:00
Stanislav Shwartsman
582bf84bae apply same optimization to disasm as well 2013-10-10 21:00:26 +00:00
Stanislav Shwartsman
37a3a76cbb optimize old disasm code 2013-10-07 19:23:19 +00:00
Stanislav Shwartsman
d68a7ca953 add option to skip mem datasize printing in disasm 2013-10-07 19:12:12 +00:00
Stanislav Shwartsman
cb0eee9456 disasm fixes 2013-10-07 19:02:53 +00:00
Stanislav Shwartsman
059769e2a6 disasm bug fixes 2013-10-06 20:42:13 +00:00
Stanislav Shwartsman
e55611df21 disasm fixes 2013-10-06 19:04:52 +00:00
Stanislav Shwartsman
add8eea761 disasm bug fixes 2013-10-06 18:37:56 +00:00
Stanislav Shwartsman
fd370a4d41 fixes in disasm, added example of using bxInstruction_c disasm into dbg_main.cc (commented out for now) 2013-10-05 19:32:09 +00:00
Stanislav Shwartsman
d4bfbffdbb disasm fixes 2013-10-05 08:34:09 +00:00
Stanislav Shwartsman
5842d09434 rename call_far and ret_far opcodes to converge between two disasm modules 2013-10-04 17:47:52 +00:00
Stanislav Shwartsman
85b0402668 fixes for disasm 2013-10-02 19:23:34 +00:00
Stanislav Shwartsman
5331e8d4d3 rename disasm variable 2013-10-01 20:12:28 +00:00
Stanislav Shwartsman
2526282ed9 small additions for avx512 2013-09-20 18:27:33 +00:00
Stanislav Shwartsman
7297323c69 First step of AVX512 support implementation (simplest) 
decode and implement KMASK manipulation instructions
disasm: coming soon
 2013-09-08 19:19:16 +00:00
Stanislav Shwartsman
25f99f76c3 remove test registers from disasm as well 2013-08-23 05:54:51 +00:00
Stanislav Shwartsman
852b5c3749 implemented SHA new instructions announced in recent Intel SDM extensions document rev015 2013-07-24 18:44:22 +00:00
Stanislav Shwartsman
2638c1136a Add RDRAND/RDSEED instructions support (+ disasm) 
Of course no true random numbers will be generated - use standard "C" rand() function as stub.
In future it will be possible to improve (using another random generator) or even use real rdrand/rdseed intrinsics
 2012-10-09 15:16:48 +00:00
Stanislav Shwartsman
dbb23aed43 close another SMC hole 2012-10-01 18:19:09 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
df90b80352 set of small cpu fixes 2012-08-09 13:11:25 +00:00
Stanislav Shwartsman
be76f38b46 correct MOVBE decoding with prefix 0x66, also correct ADX decoding 2012-08-08 20:11:27 +00:00
Volker Ruppert
53438e92c6 - fixes based on Debian patches by Guillem Jover 
- set SHELL variable with configure script
  - add '--tag CXX' argument to libtool calls
 2012-07-14 07:01:43 +00:00