Stanislav Shwartsman
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0325c120b2
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Separate PAUSE instruction from regular NOP
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2009-01-27 20:29:05 +00:00 |
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Stanislav Shwartsman
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9929e6ed78
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- updated FSF address
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2009-01-16 18:18:59 +00:00 |
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Stanislav Shwartsman
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0ff68a2aa2
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Fixed XSAVE decode in x86-64 mode
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2009-01-10 16:01:55 +00:00 |
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Stanislav Shwartsman
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7566faf948
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A bit simplify FPU decoding
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2008-09-16 18:28:53 +00:00 |
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Stanislav Shwartsman
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a0e395188f
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Fixed merge error
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2008-08-29 20:43:05 +00:00 |
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Stanislav Shwartsman
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b96f78dc0a
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Some kind of big change in fetchdecode tables invented in order to compress the tables for better host data cache utilization
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2008-08-29 19:23:03 +00:00 |
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Stanislav Shwartsman
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70c7c5ceca
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Use LOAD_Eb approach to remove duplicated GbEb methods
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2008-08-11 20:34:05 +00:00 |
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Stanislav Shwartsman
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a8adb36dc2
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Implemented MOVBE Intel Atom(R) instruction
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2008-08-11 18:53:24 +00:00 |
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Stanislav Shwartsman
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b61017e5b6
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Split more opcodes using new LOAD technique
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2008-08-10 21:16:12 +00:00 |
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Stanislav Shwartsman
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0d90ab0478
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Completely new way to handle LD+OP cases - allows to significantly reduce number of BX_CPU_C methods
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2008-08-09 21:05:07 +00:00 |
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Stanislav Shwartsman
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0127415ba6
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Clear some duplicated arithmetic opcodes - difference only in operands order
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2008-07-13 09:59:59 +00:00 |
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Stanislav Shwartsman
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7494b8823b
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- Support of AES CPU extensions, to enable configure with
--enable-aes option
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2008-05-30 20:35:08 +00:00 |
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Stanislav Shwartsman
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ed4be45a8b
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Split shift/rotate opcodes in 32-bit mode and 64-bit mode
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2008-05-02 22:47:07 +00:00 |
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Stanislav Shwartsman
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81deffd65d
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More fetchdecode fixes
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2008-04-30 21:32:33 +00:00 |
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Stanislav Shwartsman
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e5b6f90b62
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some fetchdecode fixes
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2008-04-30 21:07:12 +00:00 |
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Stanislav Shwartsman
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06c6ac0060
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- Fixed effective address wrap in 64-bit mode with 32-bit address size
- Fixed SMSW instruction in 32-bit and 64-bit modes
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2008-04-28 18:18:08 +00:00 |
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Stanislav Shwartsman
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64f2489afb
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Correctly implement opcode group G11 i.e. instructions C6 and C7 should @UD when modrm nnn field != 0 (1st instr in the group
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2008-04-24 21:52:28 +00:00 |
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Stanislav Shwartsman
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a055323e18
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Handle undocumented FPU opcodes
Support for BIG real mode CS.LIMIT check
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2008-04-21 14:17:04 +00:00 |
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Stanislav Shwartsman
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419dc57dbd
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Complete MASKMOVDQU decoding fix
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2008-04-16 05:56:55 +00:00 |
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Stanislav Shwartsman
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4f3f8608f7
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Fixed MASKMOVDQU instruction decoding
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2008-04-16 05:41:43 +00:00 |
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Stanislav Shwartsman
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76a8812876
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correct some opcode aliases
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2008-04-12 10:08:43 +00:00 |
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Stanislav Shwartsman
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5826e2843a
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Inline pop/push functions
Store only single byte of opcode in b1() - speedup shift instructions
Code cleanups
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2008-04-05 17:51:55 +00:00 |
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Stanislav Shwartsman
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2aaafa76a2
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Reorganize fetchdecode tables with another level of redirection - a leap toward future improvements
Currently no speedup and no slowdown - about the same results on my Bochs benchmarking
A lot of code reorganization in fetchdecode
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2008-04-04 22:39:45 +00:00 |
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Stanislav Shwartsman
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167c7075fb
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Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code
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2008-03-22 21:29:41 +00:00 |
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Stanislav Shwartsman
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7e490699d4
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Removing hooks for not-implemented SSE4A from the Bochs code.
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2008-03-21 20:04:42 +00:00 |
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Stanislav Shwartsman
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946b7a369d
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Added const to fetchPtr in cpu functions
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2008-03-03 15:16:46 +00:00 |
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Stanislav Shwartsman
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405fcfd75d
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Reorganize 3-byte opcode tables - bigger tables but easier to maintain them
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2008-02-29 03:02:03 +00:00 |
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Stanislav Shwartsman
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8615022962
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Added first stubs for XSAVE/XRESTOR implementation
Disassemble XSAVE/XRSTOR instructions (4 instructions)
Update CHANGES - a bit speculatively
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2008-02-12 22:41:39 +00:00 |
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Stanislav Shwartsman
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a2897933a3
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white space cleanup
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2008-02-02 21:46:54 +00:00 |
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Stanislav Shwartsman
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37fbb82baa
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Cleanups. Move bxInstruction_c definition to separate file instr.h
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2008-01-29 17:13:10 +00:00 |
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Stanislav Shwartsman
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7b80c5f481
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I merged and succeded to remove some similar execution functions - less code, less chance for branch misprediction
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2008-01-25 19:34:30 +00:00 |
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Stanislav Shwartsman
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c6fd4ebf94
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Split CALL_Ev and JMP_Ev methods
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2008-01-12 16:40:38 +00:00 |
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Stanislav Shwartsman
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c9932e97eb
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Fixes in resolve.cc -> reduce amount of resolve functions even more
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2007-12-18 21:41:44 +00:00 |
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Stanislav Shwartsman
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1e843cb462
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Decode SSE4A
Rework immediate bytes decoding to make it faster
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2007-12-15 17:42:24 +00:00 |
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Stanislav Shwartsman
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3a6d714398
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Split for JMP_Ew/Ed opcodes from Grp5
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2007-12-14 23:15:52 +00:00 |
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Stanislav Shwartsman
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adda3befd3
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Trace cache optimization merged
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2007-12-09 18:36:05 +00:00 |
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Stanislav Shwartsman
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39b2680110
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Fixed compilation error when x86-64 emualtion disabled
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2007-11-29 22:22:24 +00:00 |
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Stanislav Shwartsman
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8cfd17202a
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some simple SSE code optimizations
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2007-11-27 22:12:45 +00:00 |
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Stanislav Shwartsman
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c51888f43f
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Split last BxLockable opcodes -> this allows to eliminate mod==0xc0 check from fetchdecode of every instruction
reduce ACPU.CC dependencies - now that file doesn't depend of CPU
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2007-11-25 20:22:10 +00:00 |
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Stanislav Shwartsman
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83f6eb6945
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Changes copyrights for the files I wrote :)
Also split EqId G1 group for x86-64
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2007-11-17 23:28:33 +00:00 |
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Stanislav Shwartsman
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5ec15df46d
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Split more opcodes EbIb opcodes
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2007-11-17 18:08:46 +00:00 |
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Stanislav Shwartsman
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d5a58e1df2
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Split more opcodes - G3 group
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2007-11-17 16:20:37 +00:00 |
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Stanislav Shwartsman
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d9e58bd598
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split11b on opcode tables level - split almost eevery splittable instruction
will be continued
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2007-11-17 12:44:10 +00:00 |
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Stanislav Shwartsman
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abe3f4c5c2
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Split one more opcode
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2007-11-16 21:43:23 +00:00 |
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Stanislav Shwartsman
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565e7f9868
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Merge common fetchdecode groups. Add more comments to fetchdecode tables
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2007-11-16 18:34:14 +00:00 |
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Stanislav Shwartsman
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393018cdf8
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More split11b
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2007-11-16 17:45:58 +00:00 |
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Stanislav Shwartsman
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351244d1ea
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Rename splitmod11b methods
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2007-11-16 08:30:22 +00:00 |
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Stanislav Shwartsman
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be9ad60ef3
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cleanups
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2007-10-11 22:44:17 +00:00 |
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Stanislav Shwartsman
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dbb91069f4
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Added SSE4_2 instructions emulation
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2007-10-01 19:59:37 +00:00 |
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Stanislav Shwartsman
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0dc4badfbb
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Added SSE4A and SSE4_2 to disassembler
Implemented POPCNT instruction
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2007-09-19 19:38:10 +00:00 |
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