running with multi-way caches. Since we know the ops will mostly
hit as we just dirtied those lines a single hit op is cheaper than
an index op for each way.
only allowing one mapping at a time instead of mapping uncached. Done
by removing conflicting mappings from the pmap when entering a new
mapping. UVM will remember and re-fault the requested page when needed
for the original mapping. Originally done to support our internal machine
that does not support uncached memory completely. Not enabled by default
currently. It may make sense to try on the cobalt or sgi ports.
the page is wired down. Flushing both halves of a wired TLB entry resulted
in hangs when in programs called for and released kernel memory
soon after being invoked. In particular, we see this when single-stepping
a process using GDB.
It would be better if we could arrange to use both halves of the TLB
entry for the PCB, but for some reason we frequently end up with things
on an odd page boundary.
pmap_enter() cannot allocate the segmap return failure if PMAP_CANFAIL
instead of sleeping. Otherwise panic. Both alpha and i386 do this. Do
not pmap_enter_pv() until after this is done so the data structures are
not partially allocated. This should prevent pmap_page_protect() from
getting stuck when called from pagedaemon.
for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write. (Writing can, of
course, be quite dangerous.)
with a MIPS4 option at this point -- all the code except for one single
spot is conditionalized with MIPS3. So, don't even pretend about
MIPS4 for now, until it all gets cleaned up.
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.
you do not save it and pass it along in rval the system will start
to fail running user programs. This finishes the suggestion by cgd to
not save some registers on syscall entry.
that the page being zero'd was not completed and that page zeroing
should be aborted. This may be used by machine-dependent code doing
slow page access to reduce the latency of running a process that has
become runnable while in the middle of doing a slow page zero.
in syscall() anymore. By defition, processor was in SR_INT_IE turn
on prior to have syscall exception. MIPS1 assembler hook arranges
to enable the bit for its own. MIPS3 does the same effect by
turning off EXL bit.
fact the direct mapped cache makes address alias effect.
- Just turn on processor master interrupt mask IEc (SR_INT_IE) bit prior
to call syscall() kernel entry point. IEp is always 1 in this case
by defition.
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).
abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).
XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h
a whole 0.01us in lmbench lat_syscall null on our 250Mhz QED system.
$at is still saved just to be safe, although it looks like it does
not need to be. $v1 is used in syscall(), although I'm not sure why.
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.
it look at casual inspection like 1 nop is needed but play other tricks.
Still have reduced by 1 nop. Hopefully this covers the NEC 41[x]1. Could
not find info for those processors.
in the non-MULTIPROCESSOR case (LOCKDEBUG requires it). Scheduler
lock is held upon entry to mi_switch() and cpu_switch(), and
cpu_switch() releases the lock before returning.
Largely from Bill Sommerfeld, with some minor bug fixes and
machine-dependent code hacking from me.
