msgbuf. Note that old 'dmesg' and 'syslogd' binaries will continue running,
though old 'dmesg' binaries will output a few bytes of junk at the start of
the buffer, and will miss a few bytes at the end of the buffer.
Compute CPU speed(MHz) and loop multiplier for DELAY() based on
counting empty loop between mcclock ticks. New global: cpu_mhz.
Change pmax/pmax/machdep.c to build baseboard model names from cpu_mhz.
Set 'cpuspeed' for more realistic DELAY() on mips3 models.
Mips CPU constants, testing, and calibration from D. Sean Davidson
<davidson@zk3.dec.com> and Simon Burge <simonb@telstra.com.au>.
* prototype and definition for pmap_activate(p). Updates the segtab,
and changes the active ASID if p == curproc.
* Make reserved fixed-address (UADDR) kernelstack PTEs global,
so we still have a kernel stack after pmap_activate() on curproc.
* make KSEG2 mappings for p_addr global (see above.)
Seems to detune contextswitch and NTP resolution (by 60 ms), but
thepmap_activate() interface is mandatory. Needs more thought.
of cache-index incompatible virtual mappings for a physical page may be
required for hardware without secondary (level 2) cache to detect and
correct virtual coherency problems. I'm not sure this is really needed
anymore, since pmap_prefer() took care of of the cache-index
incompatible mappings that I have seen. Count the times a page is
cache inhibited in enter_stats if DEBUG.
Wait for memory instead of panic() on failure to allocate a page for the
segtab or segmap [from OpenBSD arc port]. Also check for malloc()
failure on allocation of a new pv entry and panic().
Increment resident_count when adding a new page to a pmap [also from
OpenBSD]. Process resident size is now valid.
cache flush operations required on a virtually-indexed, physically-tagged
mips3 with no L2 cache to provide cache-coherence exceptions.
(Similar to what's needed with a virtually-indexed, virtually-tagged cache.)
faults. Use curpcb, which always points to the current pcb. If curproc
was NULL when the kernel faulted, the trap handling would fault recursively
and the kernel stack would overflow.
Has unrolled loop for aligned-to-aligned copy.
Notes:
1. this code tuned for DEC 5000/200. ioasic decstations do more unaligned
copies. Better than old non-unrolled loop, but could be improved.
2. Undoes changes made for MIPS3 with comment implying an r4000 TLB bug.
We can't reproduce this on 5000/150 (jonathan) or 5000/50 (mhitch).
Calls to previous bcopy with a bad address show similar symptoms,
reporting a trap in bcopy() after bcopy() has returned. Same thing??
Needs re-checking on an r4000 with no L2 cache.
sigcode():
executed from user-space stack.
mips1_cpu_switch_resume, mips3_cpu_switch_resume:
arguments passed in via v0, t0, t1 (outlined from cpu_switch())
mips3_VCED(), mips3_VCEI():
called from exception-vector code without any register save,
$at, $ra are live.
undone by rev 1.7:
>redo pmax/include/reg.h
>so that the definitions needed by locore.S are in a separate file,
>pmax/include/regnum.h.
* Add explicit `#include <mips/regnum.h>' where symbolic offsets
into a mips trapframe or struct reg are used..
Add DDB interface to /sys/arch/mips/mips..
Rework heuristic stack traceback to work with DDB.
Add hooks to print exception log from DDB.
Add hooks from pmax console drivers: call Debugger()
after break from serial console, or 'DO' key from LK-xxx.
ktlbmiss on the kernel stack. It was showing the temporary SP, not the
original SP.
Add a display of the first few wired entries of the TLB so when the ktblmiss
occurs, the TLB entries mapping the kernel stack can be verified.
* cpuregs.h:
rename remaining VMMACH_xxx TLB macros to MIPS_TLB_xxx.
Add compile-time MIPS3-only, compile-time MIPS1-only, and
runtime (both) definitions for number of TLB ASIDs (tlb pids)
and shift count to extract a TLB pid.
* locore.h:
Delete unused vector slot for indexed TLB writes.
mips1 and mips3 TLBs are different enough that we have
to break them out at the caller anyway.
* Add compile-time MIPS3-only andcompile-time MIPS1-only
macros to call locore functions directly by name.
Use the existing method table only if
* mips/mips_machdep.c, mips/trap.c, mips/pmap.c, pmax/machdep.c:
Use MIPS3_ or MIPS1_ specific names for TLB pids in
mips3 and mips1 specific code paths (e.g., creating the kernel stack
for process 0).
Add `options MIPS3' to pmax/conf/GENERIC.
Remove unused debug procedure I forgot to remove previously.
Consolidate the vm_page_free1() calls in pmap_release(). Duplicate code
was a result of the way I merged the MIPS3 support from the pica pmap.c.
Enhance the comment on flushing the cache when releasing the segmap pages,
and add a comment about the currently unused code to uncache pages in
pmap_enter_pv().
unsigned cause register wouldn't have worked.
Add missing ')' in trapdump that shows up when compiled with DEBUG.
Fix (unfix?) previous change to printf formats in mips3_dump_tlb: vad_to_pfn
is now consistant with single-CPU and merged-CPU support.
* cpuregs.h:
Delete unused VMMACH_ names (e.g., duplicates of PTE bits in pte.h).
Change remaining VMMACH_xxx names to MIPS1_xxx or MIPS3_xx.
Fold remaining compile-time definitions into a single #ifdef MIPS3.
* Use MIPS1_ names in locore_r2000.S, mips3_ names in locore_r4000.S
* Garbage-collect MachHitFlushDCache()
* psl.h:
use MIPS1_, MIPS3_ symbolic names for Cause register bits.
change _R3K to MIPS1_, _R4K to MIPS3. Conditionalize for mips1 only,
mips3 only, or when both are defined, use runtime CPUISMIPS3 test.
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.
Remove cpu-specific routines from locore.S and add them to locore_r2000.S
and locore_r4000.S. Add entries in locore jump vector table for switch_exit()
and the cpu_switch() context resume.
Add offsets into the jump vector to genassym.cf for use in locore.S.
Use same cachesize variables for mips1 and mips3, and rename the variables
per Jonathan's request.
the stack frame when usermode interrupt occurs. The interrupt may have
modified the PC [such as sendsig()]. This got dropped with the stackframe
changes.
Remove old code now that the new version is working.
Correct typo for 16K cache (R4400).
Align the saved AT register location; seems to hang if not aligned on 8
byte boundry.
similar design and code by Jason Thorpe and Jonathan Stone.
NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.
mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.
mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.
mips/include/mips1_pte.h:
mips1 TLB bit definitions.
mips/include/mips3_pte.h:
mips3 TLB bit definitions.
mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.
mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.
mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.
mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)
mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.
mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().
pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
Move mips-specific pmap definitions (PMAP_PREFER for mips3, declaratin
of pmap_bootstrap() for the system-specific machdep.c) from
arch/pmax/include/pmap.h to arch/mips/include/pmap.h.
* Move declaration of locore communcation variables (CPU family,
cache sizes, etc) to mips/include/locore.h. Delete from
pmax/include/cpu.h and older versions from pica/include/cpu.h.
* Move definitions of CLKF_BASEPRI, CLKF_USERMODE to mips/include/cpu.
* Delete duplicate definitions in pica/include/cpu.h, pmax/include/cpu.h.
Change pmax/include/psl.h to just do #include <mips/psl.h>.
pmax/include/psl.h would go away completely if it wasn't stil required
by compat/common/kern_exit_43.c.
processing from generic trap processing, _FORKBRAINDAMAGE is gone -
user process entered through proc_trampoline(), mini-debugger from pica
port.
More merged MIPS1/MIPS3 support for DECstations.
proc_trampoline(); move away from UADDR access to user structure.
From Toru Nishimura: exception trapframe changes, mini-debugger from pica
port, separate out syscall exception.
DECstation MIPS3 support: wbflush() is cpu-dependent, MIPS3 level 2 cache
support.
interrupt-enable bit in the status register, and all lower bits.
Can be used for spl{bio,net,tty,clock,statclock} on machines where
devices are wried to mips hard-interrupt levels in ascending bit order
so as to match the BSD spl.9 ordering.
Some of the stuff (e.g., rarpd, bootpd, dhcpd etc., libsa) still will
only support Ethernet. Tcpdump itself should be ok, but libpcap needs
lot of work.
For the detailed change history, look at the commit log entries for
the is-newarp branch.
Fixes profiling for non-underscore-prepending toolchains
(elf, e.g., shared libs), and breaks a.out/ecoff toolchains.
May break mips kernel profiling too. Needs more thought, since the
original intent of __mcount vs ___mcount on mips date back to pre-1.0 days.
* handle interpreters with nonzero virtual address of entry-point:
subtract p_vaddr from computed entrypoint, as the mips elf exec did.
* Add #ifdef ELF_INTERP_NON_RELOCATABLE/#endif around the code
that tries to choose a `good' address at which to load an interpreter,
if none was set by the emul probe function.
(the address chosen could be improved to avoid fragmenting the
process virtual address space).
* define ELF_INTERP_NON_RELOCATABLE in machine/elf_machdep.h for mips CPUs,
which currently use a GNU-derived ld.so.
ELF_INTERP_NON_RELOCATABLE is not necessary for native NetBSD/alpha ELF
binaries. It may be required for GNU-derived ELF dynamic loaders (Linux/i386?)
mips_r2000_, mips_R2000_ -> mips1_
mips_r4000_, mips_R4000_ -> mips3_
(which are also, for mnemonic reasons, consistent with gcc flag usage,
rather than using mipsI_ and mipsIII_).