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1263 Commits

Author SHA1 Message Date
simonb
4a1086db83 There's 8 interrupt_status_N registers, not 7. 2002-03-28 12:49:55 +00:00
simonb
de2d1df3a9 Remove the comment that says this is for PCI busses only. 2002-03-23 14:20:41 +00:00
simonb
8e5ab10b05 Add generic chipset memory and I/O "bus" functions for mips, based on 
algor/pci/pci_alignstride_bus_{io,mem}_chipdep.c.
 2002-03-23 14:19:18 +00:00
chs
fb88d3b0ba add missing cache flushes in pmap_protect(). fixes PR 15965. 2002-03-20 02:50:19 +00:00
simonb
267b8c65f5 Define all CPU types if _LKM is defined; fixes problems building LKM's 
as noted by FUKAUMI Naoki on port-mips.
 2002-03-19 00:53:46 +00:00
simonb
91785659ba Generic PCI/ISA machdep headers for mips; copied from the algor port. 2002-03-18 03:08:09 +00:00
simonb
7e2ca5e1a8 Copy the algor bus_dma.c for use as a generic bus_dma implementation for 
other MIPS ports.
 2002-03-18 02:32:54 +00:00
simonb
e64d2d9708 Oops, balance #ifdef/#endif _KERNEL. 2002-03-18 01:01:54 +00:00
simonb
d9aac5ef07 Add generic MIPS bus_space and bus_dma headers; these are a straight 
split of the algor <machine/bus.h>.
 2002-03-18 00:32:21 +00:00
manu
c51e325123 Replaced PS_STRINGS by p->p_psstr 2002-03-17 20:54:09 +00:00
simonb
9be5709e65 Fix some whitespace/indentation niggles. 2002-03-17 07:38:28 +00:00
simonb
17162f3d40 Add R4400 reg 0x60 to the MIPS CPU table. 
From PR port-mips/15894 from Thilo Manske.
 2002-03-13 13:18:58 +00:00
simonb
22db14d9e1 All the mips ports had an identical procfs_machdep.c, so use a common 
file under arch/mips/mips.
 2002-03-13 02:55:10 +00:00
uch
552fdb7e1b make this compile and work with MIPS3_5900. 2002-03-11 16:39:39 +00:00
thorpej
a180cee23b Pool deals fairly well with physical memory shortage, but it doesn't 
deal with shortages of the VM maps where the backing pages are mapped
(usually kmem_map).  Try to deal with this:

* Group all information about the backend allocator for a pool in a
  separate structure.  The pool references this structure, rather than
  the individual fields.
* Change the pool_init() API accordingly, and adjust all callers.
* Link all pools using the same backend allocator on a list.
* The backend allocator is responsible for waiting for physical memory
  to become available, but will still fail if it cannot callocate KVA
  space for the pages.  If this happens, carefully drain all pools using
  the same backend allocator, so that some KVA space can be freed.
* Change pool_reclaim() to indicate if it actually succeeded in freeing
  some pages, and use that information to make draining easier and more
  efficient.
* Get rid of PR_URGENT.  There was only one use of it, and it could be
  dealt with by the caller.

From art@openbsd.org.
 2002-03-08 20:48:27 +00:00
tsutsui
3c8b0446fe Change type of dumpmag to u_int32_t since it is actually 
a 32bit unsigned magic number.
As per discussion on tech-kern, and fixes port-sparc64/11949.
 2002-03-06 13:10:18 +00:00
simonb
1c904f9d33 Use MIPS_PHYS_TO_KSEG1 instead of cfe's PHYS_TO_K1 macro. 2002-03-06 09:32:04 +00:00
simonb
2bf916e97d Implement a clkread() function for microtime() using a multu/mfhi 
sequence using the reciprocal of the delay divisor to perform the
division.
Set the cp0 compare register so that it doesn't trigger interrupts and
reset the cp0 count register in the hardclock interrupt handler.
 2002-03-06 07:47:57 +00:00
simonb
feb24029e7 Add the offset of ci_divisor_delay in struct cpu_info. 2002-03-06 07:32:15 +00:00
simonb
78c9211fca Add a field for the reciprocal of the divisor delay for use by microtime. 2002-03-06 07:31:38 +00:00
simonb
3fe666190f Wrap long line and remove a bogus XXX comment. 2002-03-06 03:25:09 +00:00
simonb
2c68c156c5 Only include <sys/exec_ecoff.h> if EXEC_ECOFF is defined. 
Note that ELF is mandatory.
 2002-03-06 00:22:09 +00:00
simonb
3ab34324e9 Remove a few unneeded include files. 2002-03-06 00:05:06 +00:00
simonb
1b5ddfe411 Add support for the on-chip peripherals on the Broadcom SiByte SB1250 CPU 
and support routines for the Broadcom CFE (Common Firmware Environment).

This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
 2002-03-05 23:46:40 +00:00
simonb
f1dbc97679 Not used anymore. 2002-03-05 16:08:55 +00:00
simonb
811ee92532 Add support for MIPS32 and MIPS64 architectures: 
- Build mips3/5900/32/64 support subroutines.
 - Move arch/mips/mips/fp.S to central location.
 - Move NOFPU to opt_cputype.h.
 2002-03-05 16:08:00 +00:00
simonb
f340c57568 Values related to the MIPS32/MIPS64 Privileged Resource Architecture 
(from Broadcom Corp).
 2002-03-05 16:07:10 +00:00
simonb
9ac7c86a0f Adjust for 5900 include file changes. 2002-03-05 16:06:04 +00:00
simonb
3f2f4c9bf6 r5900_vector_init() is in mips_machdep.c now. 2002-03-05 16:05:26 +00:00
simonb
dd756c0ca5 Rename <mips/r5900/cpuregs.h> to <mips/r5900regs.h> and remove some 
content no longer needed.
 2002-03-05 16:04:57 +00:00
simonb
fcdc111c1a Cosmestic changes (more like the mips3+ code). 2002-03-05 16:03:22 +00:00
simonb
c5d34b4371 Remove the number of TLB entries for different rx39 CPUs - this info 
is in the table in mips_machdep.c now.
 2002-03-05 16:02:48 +00:00
simonb
c6bcfb2589 Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Bump the Sysmap size a little for large-memory machines.
XXX: still need work, especially in pmap_procwr().
 2002-03-05 16:01:25 +00:00
simonb
0f9c00fc2e Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - ANSIfy.
 2002-03-05 15:57:20 +00:00
simonb
fa9c08ab16 Remove HPCMIPS_FLUSHCACHE_XXX debug code. 
Remove old unused exception frame unwind code.
Change a MIPS3 check to a MIPS3_PLUS check.
ANSIfy.
 2002-03-05 15:55:41 +00:00
simonb
278bfc1c02 Add support for MIPS32 and MIPS64 architectures: 
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 2002-03-05 15:54:33 +00:00
simonb
351c1c16a6 Add support for MIPS32 and MIPS64 architectures: 
- Use a table-driven CPU detection algorithm instead of multiple
   case statements.
 - Add MIPS32/64 feature detection using the architected CP0 registers
   (from Broadcom Corp).
 - Call MD mips_machdep_cache_config() function if
   __HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
   L2 cache on some ports.
 2002-03-05 15:53:00 +00:00
simonb
ba8e2e82e4 Add support for MIPS32 and MIPS64 architectures: 
- Remove all mmu-related code that may use 32 register on mips32-style
   implementatios and move them to mipsX_subr.S - which is then included
   from mips{3,32,64,5900}_subr.S with various control defines enabled.
 - Remove local cache instruction flags
 - Add badaddr64 (from Broadcom Corp).
 2002-03-05 15:50:59 +00:00
simonb
9ed4fd257f Change a MIPS3 check to a MIPS3_PLUS check. 
XXX: I'm not 100% sure of the intent of this code - it would seem that
 it needs a run-time check of CPU ISA to be completely correct...
 2002-03-05 15:48:31 +00:00
simonb
d62813603c Check userland address and address alignent as two separate checks. 
Fix for when mips_reg_t is 64-bits.
ANSIfy.
 2002-03-05 15:46:51 +00:00
simonb
fe86ad150e Change MIPS3 checks to MIPS3_PLUS checks (XXX - still bogus!). 2002-03-05 15:44:40 +00:00
simonb
c9a3bd8900 Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Add a command to dump cp0 state.
 2002-03-05 15:43:25 +00:00
simonb
9b785c48f3 Cache ops for MIPS32/64 cpus. 2002-03-05 15:42:50 +00:00
simonb
0446046fde Add MIPS32/64 cache setup code (from Broadcom Corp). 2002-03-05 15:42:21 +00:00
simonb
cae6e0e516 Prototypes for MIPS32/64 cache ops. 2002-03-05 15:41:48 +00:00
simonb
0ff59237ca Change a MIPS3 check to a MIPS3_PLUS check (XXX - still bogus!). 2002-03-05 15:41:14 +00:00
simonb
01422aae5c Add support for MIPS32 and MIPS64 architectures: 
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 2002-03-05 15:40:10 +00:00
simonb
1d05db445d Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 2002-03-05 15:39:31 +00:00
simonb
934c4ba555 Add support for MIPS32 and MIPS64 architectures: 
Remove the unused PSL_USERCLR and BASEPRI macros.
 2002-03-05 15:38:33 +00:00
simonb
b255c47737 Add support for MIPS32 and MIPS64 architectures: 
Better cache coherency attribute macros (from Broadcom Corp).
 2002-03-05 15:37:32 +00:00
simonb
f38d391749 Add support for MIPS32 and MIPS64 architectures: 
- Add mips32 and mips64 locore function prototypes.
 - Add mips3_lw_a64() and mips3_sw_a64() for access data at any
   64bit address (from Broadcom Corp).
 - Add Broadcom and Sandcraft CPU company ids.
 2002-03-05 15:36:51 +00:00
simonb
2fab526863 Add support for MIPS32 and MIPS64 architectures: 
- Add XKPHYS macros (from Broadcom Corp).
 - Add some r5900 register bit definitions.
 - Add extra exception vector addresses for mips32/mips64 and r5900.
 - Make the mips cp0 register definitions available from both asm and C.
 - Add some Alchemy and Sandcraft CPU ids.
 - Add r3000, tx39xx and r4x00 CPU revision ids.
 - Remove defines for the number of TLBs on some CPUs.
 2002-03-05 15:35:22 +00:00
simonb
60fe625bd0 Add support for MIPS32 and MIPS64 architectures: 
- Clean up (somewhat) mips1 vs mips3+ configuration.
   XXX:  this is still quite messy.
 - Add cpu frequency info to struct cpu_info.
 - ANSIfy.
 2002-03-05 15:34:04 +00:00
simonb
ef0fcacb94 ANSIfy. 2002-03-05 15:12:58 +00:00
simonb
8070cbd848 Add 4way 16/32-byte-line cache op primitives. 2002-03-05 14:32:26 +00:00
simonb
e8e49d677b Don't explicitly depend locore_*.S and fp.S on assym.h - this is done 
for all .S files in /sys/conf/Makefile.kern.inc.
 2002-03-05 14:28:31 +00:00
simonb
7bd5992f7a Fix for when we have 64 bit registers enabled for userland (but still 
using the o32 API).
 2002-03-05 14:23:50 +00:00
simonb
4a931bedb8 KNF whitespace. 2002-03-05 14:21:32 +00:00
simonb
59f53aab95 The 64-bit safe, ILP32 o32 model is safe with the current stdarg 
implementation.
 2002-03-05 14:18:12 +00:00
simonb
836b7ec262 Include <machine/cdefs.h> to select 32/64bit APIs. 2002-03-05 14:17:16 +00:00
simonb
b2fb45331b ANSIfy. 2002-03-05 14:08:43 +00:00
simonb
58faa5f0ca Clean up #ifdef checks a little. 2002-03-05 14:08:07 +00:00
simonb
6f0fb25121 Don't need to declare phys_map - it is declared in <uvm/uvm_extern.h>. 2002-03-04 02:43:22 +00:00
simonb
4324f37586 Use "#define<tab>". 2002-02-28 03:17:23 +00:00
christos
e8116a8f5b - Use DEV_ constants, instead of documenting the numbers! 
- Delete cdev_decl(mm); where appropriate, and other hand-crufting [hi powerpc!]
 2002-02-27 01:20:51 +00:00
simonb
e19a9be04b Note that "addu $x, $y, $0" is a "move" only in 32-bit mode. 
XXX: need to revisit this.
 2002-02-22 16:18:36 +00:00
simonb
2d8577fb83 Clean up some rampant code duplication wrt ieee number handling: 
- Add alignment-safe double and float unions.
 - Use the above for the __infinity and __nan constants on all
   architectures that use the standard ieee754 representation of
   those constants.
 - Add a single copy of various ieee754 math functions (frexp, isinf,
   isnan, ldexp and modf) that had numerous duplicates among the
   arch-specific directories.
 - Use the above functions on all architectures where the generic C
   versions where used.  Architectures that had local assembly
   routines are untouched (for those functions only).
 2002-02-19 13:08:12 +00:00
simonb
4a188395df Make the ddb_regs declaration an extern in db_machdep.h and declare it on 
db_interface.c.
 2002-02-15 07:32:34 +00:00
thorpej
90544559d3 Don't put `frompc' into a0 in the delay slot of the __mcount 
call; `jal __mcount' might be expanded by the assembler, and
thus a bogus `frompc' value could be passed.
 2002-02-05 07:12:20 +00:00
manu
97db5a818c Added errno translation for non native OSes emulation (IRIX, Linux, Ultrix) 2002-02-02 20:28:59 +00:00
uch
715eb97754 remove unused variable. 2002-01-30 16:10:08 +00:00
uch
e3ba66bfd4 move TX39 specific cache configuration code to cache.c 2002-01-30 16:09:29 +00:00
shin
69d0f55255 add VR4131 cache-op bug workaround code. 
we can't use Hit_WriteBack_Invalidate.
 2002-01-19 04:25:36 +00:00
soren
07e21646eb Options MIPS3_5200 and MIPS3_L2CACHE_PRESENT are gone. 2002-01-14 19:07:16 +00:00
enami
5c12da5b4a Define new macro to access FSR register and use it. 2002-01-12 01:40:36 +00:00
enami
16fc46b962 Access FSR register correctly in struct fpreg.r_regs[]. 
This fixes sshd (actually, libcrypto) failure with new-toolchain.
 2002-01-12 01:37:08 +00:00
thorpej
94f30b739f Add the BONITO_ICU_RETRYERR bit. 2002-01-09 02:35:29 +00:00
thorpej
4928315412 Update copyright. 2002-01-09 00:44:06 +00:00
thorpej
d25ffb2822 Add code to manipulate the BONITO I/O Buffer Cache. 2002-01-09 00:43:38 +00:00
shin
a0a83ff5d4 fix pasto. 
s/trunc_line/trunc_line16/
 2002-01-07 07:43:52 +00:00
takemura
eef721771a Modify only K0 bits and save other bits. (HPCMIPS_L1CACHE_DISABLE) 2002-01-04 09:26:39 +00:00
uch
e4130f57f1 _intr_suspend and _intr_resume declarations are moved to intr.h. 2002-01-02 12:36:20 +00:00
shin
b7e3f7d6e3 R4000/R4400 always detects virtual alias as if 
primary cache size is 32KB. Actual primary cache size
is ignored wrt VCED/VCEI.
 2001-12-28 04:06:06 +00:00
shin
f15b256063 check if curproc is invalid, and do panic. 
otherwise, we can't useful backtrace.
Ex. address error in interrupt handler.
 2001-12-28 02:13:14 +00:00
shin
ae12ee76a0 add #ifdef DEBUG around VCED_count etc. 2001-12-27 22:55:46 +00:00
shin
606f00a905 split VCED and VCEI. 2001-12-27 04:19:17 +00:00
shin
d00d2e4bcb simplify VCED processing. 
just write back and invalidate secondary cache line and fetch data again.
 2001-12-27 04:03:37 +00:00
takemura
490f777a1f Added Vr4131 support. 2001-12-23 13:10:46 +00:00
thorpej
51535d4bf5 Add support for dumping ELF-cormat core files. 2001-12-09 23:05:56 +00:00
atatat
b45c51b1fc Roll the rest of the ports over to the new MI kernel build machinery. 
Any problems reported by testers have been fixed, and massive
cross-compiling of kernels has shown that any problems that remain
with actually building kernels are not related to this.
 2001-12-09 05:00:40 +00:00
manu
342f5317b0 Added IRIX signal trampoline 2001-12-08 11:15:43 +00:00
uch
2c8098281b TX39, R5900 cache configuration. 2001-12-02 10:37:25 +00:00
manu
fd6a281221 Added twomissing SYSCALL_SHIFT for indirect syscall through SYS_syscall 2001-12-02 08:28:18 +00:00
manu
55c08f5ede Back out the copy of theses files to userland 2001-11-28 20:13:34 +00:00
manu
fa1e4588d9 We need to copy new SVR4 header files to /usr/include/sys... 2001-11-28 12:13:49 +00:00
manu
f73e64b4be Added support for COMPAT_IRIX 2001-11-28 11:54:15 +00:00
lukem
ecb81c3f6d - convert usage of "defopt" to "defflag" where the relevant option does 
not support a value (e.g., it's to be used as "options FOO" instead of
  "options FOO=xxx"). options that take a value were converted to
  defparam recently.
- minor whitespace & formatting cleanups
 2001-11-28 10:21:10 +00:00
nisimura
9f8ca586ad Fix a small typo in comment. 2001-11-28 08:49:19 +00:00
manu
12c949a188 Added COMPAT_IRIX (being developped, not functionnal at that time) 2001-11-26 21:38:41 +00:00
shin
3dfc0ff3ab fix pasteo. 2001-11-26 13:16:17 +00:00