Add generic MIPS bus_space and bus_dma headers; these are a straight
split of the algor <machine/bus.h>.
This commit is contained in:
simonb
parent
72cfdcede0
commit
d9aac5ef07
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/* $NetBSD: bus_dma.h,v 1.1 2002/03/18 00:32:21 simonb Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
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||||
* Foundation, Inc. and its contributors.
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||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
|
||||
* notice and this permission notice appear in all copies of the
|
||||
* software, derivative works or modified versions, and any portions
|
||||
* thereof, and that both notices appear in supporting documentation.
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||||
*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#ifndef _MIPS_BUS_DMA_H_
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#define _MIPS_BUS_DMA_H_
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#include <sys/types.h>
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/*
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* Bus DMA methods.
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*/
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/*
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* Flags used in various bus DMA methods.
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*/
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#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
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#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
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#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
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#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
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#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
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#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
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#define BUS_DMA_BUS2 0x020
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#define BUS_DMA_BUS3 0x040
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#define BUS_DMA_BUS4 0x080
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#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
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#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
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/*
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* Private flags stored in the DMA map.
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*/
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#define MIPS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */
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/* Forwards needed by prototypes below. */
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struct mbuf;
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struct uio;
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/*
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* Operations performed by bus_dmamap_sync().
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*/
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#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
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#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
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#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
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#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
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typedef struct mips_bus_dma_tag *bus_dma_tag_t;
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typedef struct mips_bus_dmamap *bus_dmamap_t;
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/*
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* bus_dma_segment_t
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*
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* Describes a single contiguous DMA transaction. Values
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* are suitable for programming into DMA registers.
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*/
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struct mips_bus_dma_segment {
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bus_addr_t ds_addr; /* DMA address */
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bus_size_t ds_len; /* length of transfer */
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bus_addr_t _ds_vaddr; /* virtual address, 0 if invalid */
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};
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typedef struct mips_bus_dma_segment bus_dma_segment_t;
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/*
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* bus_dma_tag_t
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*
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* A machine-dependent opaque type describing the implementation of
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* DMA for a given bus.
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*/
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struct mips_bus_dma_tag {
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void *_cookie; /* cookie used in the guts */
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bus_addr_t _wbase; /* DMA window base */
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bus_addr_t _physbase; /* physical base of the window */
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bus_size_t _wsize; /* size of the window */
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/*
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* DMA mapping methods.
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*/
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int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
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bus_size_t, bus_size_t, int, bus_dmamap_t *);
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void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
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int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
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bus_size_t, struct proc *, int);
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int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
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struct mbuf *, int);
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int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
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struct uio *, int);
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int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
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bus_dma_segment_t *, int, bus_size_t, int);
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void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
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void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
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bus_addr_t, bus_size_t, int);
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/*
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* DMA memory utility functions.
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*/
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int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
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bus_size_t, bus_dma_segment_t *, int, int *, int);
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void (*_dmamem_free)(bus_dma_tag_t,
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bus_dma_segment_t *, int);
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int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
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int, size_t, caddr_t *, int);
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void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
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paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
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int, off_t, int, int);
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};
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#define bus_dmamap_create(t, s, n, m, b, f, p) \
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(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
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#define bus_dmamap_destroy(t, p) \
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(*(t)->_dmamap_destroy)((t), (p))
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#define bus_dmamap_load(t, m, b, s, p, f) \
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(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
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#define bus_dmamap_load_mbuf(t, m, b, f) \
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(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
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#define bus_dmamap_load_uio(t, m, u, f) \
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(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
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#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
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(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
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#define bus_dmamap_unload(t, p) \
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(*(t)->_dmamap_unload)((t), (p))
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#define bus_dmamap_sync(t, p, o, l, ops) \
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(*(t)->_dmamap_sync)((t), (p), (o), (l), (ops))
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#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
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(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
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#define bus_dmamem_free(t, sg, n) \
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(*(t)->_dmamem_free)((t), (sg), (n))
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#define bus_dmamem_map(t, sg, n, s, k, f) \
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(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
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#define bus_dmamem_unmap(t, k, s) \
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(*(t)->_dmamem_unmap)((t), (k), (s))
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#define bus_dmamem_mmap(t, sg, n, o, p, f) \
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(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
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/*
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* bus_dmamap_t
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*
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* Describes a DMA mapping.
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*/
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struct mips_bus_dmamap {
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/*
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* PRIVATE MEMBERS: not for use my machine-independent code.
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*/
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bus_size_t _dm_size; /* largest DMA transfer mappable */
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int _dm_segcnt; /* number of segs this map can map */
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bus_size_t _dm_maxsegsz; /* largest possible segment */
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bus_size_t _dm_boundary; /* don't cross this */
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int _dm_flags; /* misc. flags */
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struct proc *_dm_proc; /* proc that owns the mapping */
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/*
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* Private cookie to be used by the DMA back-end.
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*/
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void *_dm_cookie;
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/*
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* PUBLIC MEMBERS: these are used by machine-independent code.
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*/
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bus_size_t dm_mapsize; /* size of the mapping */
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int dm_nsegs; /* # valid segments in mapping */
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bus_dma_segment_t dm_segs[1]; /* segments; variable length */
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};
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#ifdef _MIPS_BUS_DMA_PRIVATE
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int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
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bus_size_t, int, bus_dmamap_t *);
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void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
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int _bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, bus_size_t,
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struct proc *, int);
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int _bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
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int _bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
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int _bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t, bus_dma_segment_t *,
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int, bus_size_t, int);
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void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
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void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, bus_size_t,
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int);
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int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size,
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bus_size_t alignment, bus_size_t boundary,
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bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
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int _bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size,
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bus_size_t alignment, bus_size_t boundary,
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bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
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paddr_t low, paddr_t high);
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void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs,
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int nsegs);
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int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs,
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int nsegs, size_t size, caddr_t *kvap, int flags);
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void _bus_dmamem_unmap(bus_dma_tag_t tag, caddr_t kva,
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size_t size);
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paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs,
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int nsegs, off_t off, int prot, int flags);
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#endif /* _MIPS_BUS_DMA_PRIVATE */
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#endif /* _KERNEL */
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#endif /* _MIPS_BUS_DMA_H_ */
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@ -0,0 +1,487 @@
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/* $NetBSD: bus_space.h,v 1.1 2002/03/18 00:32:21 simonb Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
|
||||
* its documentation is hereby granted, provided that both the copyright
|
||||
* notice and this permission notice appear in all copies of the
|
||||
* software, derivative works or modified versions, and any portions
|
||||
* thereof, and that both notices appear in supporting documentation.
|
||||
*
|
||||
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
|
||||
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
|
||||
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
|
||||
*
|
||||
* Carnegie Mellon requests users of this software to return to
|
||||
*
|
||||
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
|
||||
* School of Computer Science
|
||||
* Carnegie Mellon University
|
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* Pittsburgh PA 15213-3890
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||||
*
|
||||
* any improvements or extensions that they make and grant Carnegie the
|
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* rights to redistribute these changes.
|
||||
*/
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#ifndef _MIPS_BUS_SPACE_H_
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#define _MIPS_BUS_SPACE_H_
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#include <sys/types.h>
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#ifdef _KERNEL
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/*
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* Turn on BUS_SPACE_DEBUG if the global DEBUG option is enabled.
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*/
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#if defined(DEBUG) && !defined(BUS_SPACE_DEBUG)
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#define BUS_SPACE_DEBUG
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#endif
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#ifdef BUS_SPACE_DEBUG
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#include <sys/systm.h> /* for printf() prototype */
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/*
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* Macros for checking the aligned-ness of pointers passed to bus
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* space ops. Strict alignment is required by the MIPS architecture,
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* and a trap will occur if unaligned access is performed. These
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* may aid in the debugging of a broken device driver by displaying
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* useful information about the problem.
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*/
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#define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \
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((((u_long)(p)) & (sizeof(t)-1)) == 0)
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#define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \
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({ \
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if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \
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printf("%s 0x%lx not aligned to %lu bytes %s:%d\n", \
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d, (u_long)(p), (u_long)sizeof(t), \
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__FILE__, __LINE__); \
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} \
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(void) 0; \
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})
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#define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t)
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#else
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#define __BUS_SPACE_ADDRESS_SANITY(p, t, d) (void) 0
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#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
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#endif /* BUS_SPACE_DEBUG */
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#endif /* _KERNEL */
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struct mips_bus_space_translation;
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/*
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* Addresses (in bus space).
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*/
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typedef u_long bus_addr_t;
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typedef u_long bus_size_t;
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/*
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* Access methods for bus space.
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*/
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typedef struct mips_bus_space *bus_space_tag_t;
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typedef u_long bus_space_handle_t;
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struct mips_bus_space {
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/* cookie */
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void *bs_cookie;
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/* mapping/unmapping */
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int (*bs_map)(void *, bus_addr_t, bus_size_t, int,
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bus_space_handle_t *, int);
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void (*bs_unmap)(void *, bus_space_handle_t, bus_size_t,
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int);
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int (*bs_subregion)(void *, bus_space_handle_t, bus_size_t,
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bus_size_t, bus_space_handle_t *);
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/* MIPS SPECIFIC MAPPING METHOD */
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int (*bs_translate)(void *, bus_addr_t, bus_size_t, int,
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struct mips_bus_space_translation *);
|
||||
int (*bs_get_window)(void *, int,
|
||||
struct mips_bus_space_translation *);
|
||||
|
||||
/* allocation/deallocation */
|
||||
int (*bs_alloc)(void *, bus_addr_t, bus_addr_t,
|
||||
bus_size_t, bus_size_t, bus_size_t, int,
|
||||
bus_addr_t *, bus_space_handle_t *);
|
||||
void (*bs_free)(void *, bus_space_handle_t, bus_size_t);
|
||||
|
||||
/* get kernel virtual address */
|
||||
void * (*bs_vaddr)(void *, bus_space_handle_t);
|
||||
|
||||
/* mmap for user */
|
||||
paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int);
|
||||
|
||||
/* barrier */
|
||||
void (*bs_barrier)(void *, bus_space_handle_t,
|
||||
bus_size_t, bus_size_t, int);
|
||||
|
||||
/* read (single) */
|
||||
uint8_t (*bs_r_1)(void *, bus_space_handle_t, bus_size_t);
|
||||
uint16_t (*bs_r_2)(void *, bus_space_handle_t, bus_size_t);
|
||||
uint32_t (*bs_r_4)(void *, bus_space_handle_t, bus_size_t);
|
||||
uint64_t (*bs_r_8)(void *, bus_space_handle_t, bus_size_t);
|
||||
|
||||
/* read multiple */
|
||||
void (*bs_rm_1)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint8_t *, bus_size_t);
|
||||
void (*bs_rm_2)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint16_t *, bus_size_t);
|
||||
void (*bs_rm_4)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint32_t *, bus_size_t);
|
||||
void (*bs_rm_8)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint64_t *, bus_size_t);
|
||||
|
||||
/* read region */
|
||||
void (*bs_rr_1)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint8_t *, bus_size_t);
|
||||
void (*bs_rr_2)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint16_t *, bus_size_t);
|
||||
void (*bs_rr_4)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint32_t *, bus_size_t);
|
||||
void (*bs_rr_8)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint64_t *, bus_size_t);
|
||||
|
||||
/* write (single) */
|
||||
void (*bs_w_1)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint8_t);
|
||||
void (*bs_w_2)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint16_t);
|
||||
void (*bs_w_4)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint32_t);
|
||||
void (*bs_w_8)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint64_t);
|
||||
|
||||
/* write multiple */
|
||||
void (*bs_wm_1)(void *, bus_space_handle_t, bus_size_t,
|
||||
const uint8_t *, bus_size_t);
|
||||
void (*bs_wm_2)(void *, bus_space_handle_t, bus_size_t,
|
||||
const uint16_t *, bus_size_t);
|
||||
void (*bs_wm_4)(void *, bus_space_handle_t, bus_size_t,
|
||||
const uint32_t *, bus_size_t);
|
||||
void (*bs_wm_8)(void *, bus_space_handle_t, bus_size_t,
|
||||
const uint64_t *, bus_size_t);
|
||||
|
||||
/* write region */
|
||||
void (*bs_wr_1)(void *, bus_space_handle_t, bus_size_t,
|
||||
const uint8_t *, bus_size_t);
|
||||
void (*bs_wr_2)(void *, bus_space_handle_t, bus_size_t,
|
||||
const uint16_t *, bus_size_t);
|
||||
void (*bs_wr_4)(void *, bus_space_handle_t, bus_size_t,
|
||||
const uint32_t *, bus_size_t);
|
||||
void (*bs_wr_8)(void *, bus_space_handle_t, bus_size_t,
|
||||
const uint64_t *, bus_size_t);
|
||||
|
||||
/* set multiple */
|
||||
void (*bs_sm_1)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint8_t, bus_size_t);
|
||||
void (*bs_sm_2)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint16_t, bus_size_t);
|
||||
void (*bs_sm_4)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint32_t, bus_size_t);
|
||||
void (*bs_sm_8)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint64_t, bus_size_t);
|
||||
|
||||
/* set region */
|
||||
void (*bs_sr_1)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint8_t, bus_size_t);
|
||||
void (*bs_sr_2)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint16_t, bus_size_t);
|
||||
void (*bs_sr_4)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint32_t, bus_size_t);
|
||||
void (*bs_sr_8)(void *, bus_space_handle_t, bus_size_t,
|
||||
uint64_t, bus_size_t);
|
||||
|
||||
/* copy */
|
||||
void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t,
|
||||
bus_space_handle_t, bus_size_t, bus_size_t);
|
||||
void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t,
|
||||
bus_space_handle_t, bus_size_t, bus_size_t);
|
||||
void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t,
|
||||
bus_space_handle_t, bus_size_t, bus_size_t);
|
||||
void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t,
|
||||
bus_space_handle_t, bus_size_t, bus_size_t);
|
||||
};
|
||||
|
||||
/*
|
||||
* Translation of an MIPS bus address; INTERNAL USE ONLY.
|
||||
*/
|
||||
struct mips_bus_space_translation {
|
||||
bus_addr_t mbst_bus_start; /* start of bus window */
|
||||
bus_addr_t mbst_bus_end; /* end of bus window */
|
||||
paddr_t mbst_sys_start; /* start of sysBus window */
|
||||
paddr_t mbst_sys_end; /* end of sysBus window */
|
||||
int mbst_align_stride;/* alignment stride */
|
||||
int mbst_flags; /* flags; see below */
|
||||
};
|
||||
|
||||
#ifdef _KERNEL
|
||||
/*
|
||||
* Utility macros; INTERNAL USE ONLY.
|
||||
*/
|
||||
#define __bs_c(a,b) __CONCAT(a,b)
|
||||
#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size)
|
||||
|
||||
#define __bs_rs(sz, tn, t, h, o) \
|
||||
(__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"), \
|
||||
(*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o))
|
||||
|
||||
#define __bs_ws(sz, tn, t, h, o, v) \
|
||||
do { \
|
||||
__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \
|
||||
(*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v); \
|
||||
} while (0)
|
||||
|
||||
#define __bs_nonsingle(type, sz, tn, t, h, o, a, c) \
|
||||
do { \
|
||||
__BUS_SPACE_ADDRESS_SANITY((a), tn, "buffer"); \
|
||||
__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \
|
||||
(*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c); \
|
||||
} while (0)
|
||||
|
||||
#define __bs_set(type, sz, tn, t, h, o, v, c) \
|
||||
do { \
|
||||
__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \
|
||||
(*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c); \
|
||||
} while (0)
|
||||
|
||||
#define __bs_copy(sz, tn, t, h1, o1, h2, o2, cnt) \
|
||||
do { \
|
||||
__BUS_SPACE_ADDRESS_SANITY((h1) + (o1), tn, "bus addr 1"); \
|
||||
__BUS_SPACE_ADDRESS_SANITY((h2) + (o2), tn, "bus addr 2"); \
|
||||
(*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt); \
|
||||
} while (0)
|
||||
|
||||
|
||||
/*
|
||||
* Mapping and unmapping operations.
|
||||
*/
|
||||
#define bus_space_map(t, a, s, f, hp) \
|
||||
(*(t)->bs_map)((t)->bs_cookie, (a), (s), (f), (hp), 1)
|
||||
#define mips_bus_space_map_noacct(t, a, s, f, hp) \
|
||||
(*(t)->bs_map)((t)->bs_cookie, (a), (s), (f), (hp), 0)
|
||||
#define bus_space_unmap(t, h, s) \
|
||||
(*(t)->bs_unmap)((t)->bs_cookie, (h), (s), 1)
|
||||
#define mips_bus_space_unmap_noacct(t, h, s) \
|
||||
(*(t)->bs_unmap)((t)->bs_cookie, (h), (s), 0)
|
||||
#define bus_space_subregion(t, h, o, s, hp) \
|
||||
(*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp))
|
||||
|
||||
#define mips_bus_space_translate(t, a, s, f, bst) \
|
||||
(*(t)->bs_translate)((t)->bs_cookie, (a), (s), (f), (bst))
|
||||
#define mips_bus_space_get_window(t, w, bst) \
|
||||
(*(t)->bs_get_window)((t)->bs_cookie, (w), (bst))
|
||||
#endif /* _KERNEL */
|
||||
|
||||
#define BUS_SPACE_MAP_CACHEABLE 0x01
|
||||
#define BUS_SPACE_MAP_LINEAR 0x02
|
||||
#define BUS_SPACE_MAP_PREFETCHABLE 0x04
|
||||
|
||||
#ifdef _KERNEL
|
||||
/*
|
||||
* Allocation and deallocation operations.
|
||||
*/
|
||||
#define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \
|
||||
(*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \
|
||||
(f), (ap), (hp))
|
||||
#define bus_space_free(t, h, s) \
|
||||
(*(t)->bs_free)((t)->bs_cookie, (h), (s))
|
||||
|
||||
/*
|
||||
* Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR.
|
||||
*/
|
||||
#define bus_space_vaddr(t, h) \
|
||||
(*(t)->bs_vaddr)((t)->bs_cookie, (h))
|
||||
|
||||
/*
|
||||
* Mmap bus space for a user application.
|
||||
*/
|
||||
#define bus_space_mmap(t, a, o, p, f) \
|
||||
(*(t)->bs_mmap)((t)->bs_cookie, (a), (o), (p), (f))
|
||||
|
||||
/*
|
||||
* Bus barrier operations.
|
||||
*/
|
||||
#define bus_space_barrier(t, h, o, l, f) \
|
||||
(*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f))
|
||||
|
||||
#define BUS_SPACE_BARRIER_READ 0x01
|
||||
#define BUS_SPACE_BARRIER_WRITE 0x02
|
||||
|
||||
|
||||
/*
|
||||
* Bus read (single) operations.
|
||||
*/
|
||||
#define bus_space_read_1(t, h, o) __bs_rs(1,uint8_t,(t),(h),(o))
|
||||
#define bus_space_read_2(t, h, o) __bs_rs(2,uint16_t,(t),(h),(o))
|
||||
#define bus_space_read_4(t, h, o) __bs_rs(4,uint32_t,(t),(h),(o))
|
||||
#define bus_space_read_8(t, h, o) __bs_rs(8,uint64_t,(t),(h),(o))
|
||||
|
||||
|
||||
/*
|
||||
* Bus read multiple operations.
|
||||
*/
|
||||
#define bus_space_read_multi_1(t, h, o, a, c) \
|
||||
__bs_nonsingle(rm,1,uint8_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_read_multi_2(t, h, o, a, c) \
|
||||
__bs_nonsingle(rm,2,uint16_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_read_multi_4(t, h, o, a, c) \
|
||||
__bs_nonsingle(rm,4,uint32_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_read_multi_8(t, h, o, a, c) \
|
||||
__bs_nonsingle(rm,8,uint64_t,(t),(h),(o),(a),(c))
|
||||
|
||||
|
||||
/*
|
||||
* Bus read region operations.
|
||||
*/
|
||||
#define bus_space_read_region_1(t, h, o, a, c) \
|
||||
__bs_nonsingle(rr,1,uint8_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_read_region_2(t, h, o, a, c) \
|
||||
__bs_nonsingle(rr,2,uint16_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_read_region_4(t, h, o, a, c) \
|
||||
__bs_nonsingle(rr,4,uint32_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_read_region_8(t, h, o, a, c) \
|
||||
__bs_nonsingle(rr,8,uint64_t,(t),(h),(o),(a),(c))
|
||||
|
||||
|
||||
/*
|
||||
* Bus write (single) operations.
|
||||
*/
|
||||
#define bus_space_write_1(t, h, o, v) __bs_ws(1,uint8_t,(t),(h),(o),(v))
|
||||
#define bus_space_write_2(t, h, o, v) __bs_ws(2,uint16_t,(t),(h),(o),(v))
|
||||
#define bus_space_write_4(t, h, o, v) __bs_ws(4,uint32_t,(t),(h),(o),(v))
|
||||
#define bus_space_write_8(t, h, o, v) __bs_ws(8,uint64_t,(t),(h),(o),(v))
|
||||
|
||||
|
||||
/*
|
||||
* Bus write multiple operations.
|
||||
*/
|
||||
#define bus_space_write_multi_1(t, h, o, a, c) \
|
||||
__bs_nonsingle(wm,1,uint8_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_write_multi_2(t, h, o, a, c) \
|
||||
__bs_nonsingle(wm,2,uint16_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_write_multi_4(t, h, o, a, c) \
|
||||
__bs_nonsingle(wm,4,uint32_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_write_multi_8(t, h, o, a, c) \
|
||||
__bs_nonsingle(wm,8,uint64_t,(t),(h),(o),(a),(c))
|
||||
|
||||
|
||||
/*
|
||||
* Bus write region operations.
|
||||
*/
|
||||
#define bus_space_write_region_1(t, h, o, a, c) \
|
||||
__bs_nonsingle(wr,1,uint8_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_write_region_2(t, h, o, a, c) \
|
||||
__bs_nonsingle(wr,2,uint16_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_write_region_4(t, h, o, a, c) \
|
||||
__bs_nonsingle(wr,4,uint32_t,(t),(h),(o),(a),(c))
|
||||
#define bus_space_write_region_8(t, h, o, a, c) \
|
||||
__bs_nonsingle(wr,8,uint64_t,(t),(h),(o),(a),(c))
|
||||
|
||||
|
||||
/*
|
||||
* Set multiple operations.
|
||||
*/
|
||||
#define bus_space_set_multi_1(t, h, o, v, c) \
|
||||
__bs_set(sm,1,uint8_t,(t),(h),(o),(v),(c))
|
||||
#define bus_space_set_multi_2(t, h, o, v, c) \
|
||||
__bs_set(sm,2,uint16_t,(t),(h),(o),(v),(c))
|
||||
#define bus_space_set_multi_4(t, h, o, v, c) \
|
||||
__bs_set(sm,4,uint32_t,(t),(h),(o),(v),(c))
|
||||
#define bus_space_set_multi_8(t, h, o, v, c) \
|
||||
__bs_set(sm,8,uint64_t,(t),(h),(o),(v),(c))
|
||||
|
||||
|
||||
/*
|
||||
* Set region operations.
|
||||
*/
|
||||
#define bus_space_set_region_1(t, h, o, v, c) \
|
||||
__bs_set(sr,1,uint8_t,(t),(h),(o),(v),(c))
|
||||
#define bus_space_set_region_2(t, h, o, v, c) \
|
||||
__bs_set(sr,2,uint16_t,(t),(h),(o),(v),(c))
|
||||
#define bus_space_set_region_4(t, h, o, v, c) \
|
||||
__bs_set(sr,4,uint32_t,(t),(h),(o),(v),(c))
|
||||
#define bus_space_set_region_8(t, h, o, v, c) \
|
||||
__bs_set(sr,8,uint64_t,(t),(h),(o),(v),(c))
|
||||
|
||||
|
||||
/*
|
||||
* Copy region operations.
|
||||
*/
|
||||
#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
|
||||
__bs_copy(1, uint8_t, (t), (h1), (o1), (h2), (o2), (c))
|
||||
#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
|
||||
__bs_copy(2, uint16_t, (t), (h1), (o1), (h2), (o2), (c))
|
||||
#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
|
||||
__bs_copy(4, uint32_t, (t), (h1), (o1), (h2), (o2), (c))
|
||||
#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
|
||||
__bs_copy(8, uint64_t, (t), (h1), (o1), (h2), (o2), (c))
|
||||
|
||||
/*
|
||||
* Bus stream operations--defined in terms of non-stream counterparts
|
||||
*/
|
||||
#define __BUS_SPACE_HAS_STREAM_METHODS 1
|
||||
#define bus_space_read_stream_1 bus_space_read_1
|
||||
#define bus_space_read_stream_2 bus_space_read_2
|
||||
#define bus_space_read_stream_4 bus_space_read_4
|
||||
#define bus_space_read_stream_8 bus_space_read_8
|
||||
#define bus_space_read_multi_stream_1 bus_space_read_multi_1
|
||||
#define bus_space_read_multi_stream_2 bus_space_read_multi_2
|
||||
#define bus_space_read_multi_stream_4 bus_space_read_multi_4
|
||||
#define bus_space_read_multi_stream_8 bus_space_read_multi_8
|
||||
#define bus_space_read_region_stream_1 bus_space_read_region_1
|
||||
#define bus_space_read_region_stream_2 bus_space_read_region_2
|
||||
#define bus_space_read_region_stream_4 bus_space_read_region_4
|
||||
#define bus_space_read_region_stream_8 bus_space_read_region_8
|
||||
#define bus_space_write_stream_1 bus_space_write_1
|
||||
#define bus_space_write_stream_2 bus_space_write_2
|
||||
#define bus_space_write_stream_4 bus_space_write_4
|
||||
#define bus_space_write_stream_8 bus_space_write_8
|
||||
#define bus_space_write_multi_stream_1 bus_space_write_multi_1
|
||||
#define bus_space_write_multi_stream_2 bus_space_write_multi_2
|
||||
#define bus_space_write_multi_stream_4 bus_space_write_multi_4
|
||||
#define bus_space_write_multi_stream_8 bus_space_write_multi_8
|
||||
#define bus_space_write_region_stream_1 bus_space_write_region_1
|
||||
#define bus_space_write_region_stream_2 bus_space_write_region_2
|
||||
#define bus_space_write_region_stream_4 bus_space_write_region_4
|
||||
#define bus_space_write_region_stream_8 bus_space_write_region_8
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||||
|
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#endif /* _MIPS_BUS_SPACE_H_ */
|
||||
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Reference in New Issue